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参数资料
| 型号： | S29GL256N80FFI023 |
| 厂商： | Spansion Inc. |
| 英文描述： | MirrorBit Flash Family |
| 中文描述： | MirrorBit闪存系列 |
| 文件页数： | 18/110页 |
| 文件大小： | 2624K |
| 代理商： | S29GL256N80FFI023 |
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May 13, 2004 27631A4
S29GLxxxN MirrorBitTM Flash Family
15
Ad va nc e
Inform ati o n
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch
used to store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to
the internal state machine. The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they
require, and the resulting output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5V, X = Don’t Care, SA = Sector
Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are AMax:A0 in word mode; AMax:A-1 in byte mode. Sector addresses are AMax:A16 in both modes.
2. If WP# = VIL, the first or last sector group remains protected. If WP# = VIH, the first or last sector will be
protected or unprotected as determined by the method described in “Write Protect (WP#)”. All sectors are
unprotected when shipped from the factory (The SecSi Sector may be factory protected depending on version
ordered.)
3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or
word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0–DQ15 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only
data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/
O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.
VersatileIOTM (VIO) Control
The VersatileIOTM (VIO) control allows the host system to set the voltage levels
that the device generates and tolerates on CE# and DQ I/Os to the same voltage
Operation
CE#
OE#
WE
#
RESET#
WP#/
ACC
Addresses
(Note 2)
DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE#
= VIL
Read
L
H
X
AIN
DOUT
DQ8–DQ14
= High-Z,
DQ15 = A-1
Write (Program/Erase)
L
H
L
H
Note 2
AIN
(Note 3)
(Note
3)
Accelerated Program
L
H
L
H
VHH
AIN
(Note 3)
(Note
3)
Standby
VCC ±
0.3 V
XX
VCC ±
0.3 V
H
X
High-Z
Output Disable
L
H
X
High-Z
Reset
X
L
X
High-Z
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