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| 型号： | S29WS128N0LBFW010 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY |
| 中文描述： | 8M X 16 FLASH 1.8V PROM, 70 ns, PBGA84 |
| 封装： | 11.60 X 8 MM, LEAD FREE, PLASTIC, FBGA-84 |
| 文件页数： | 16/95页 |
| 文件大小： | 1745K |
| 代理商： | S29WS128N0LBFW010 |
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October 29, 2004 S29WSxxxN_00_F0
23
Pre l i m i n a r y
Figure 7.2. Synchronous Read
7.3.1 Continuous Burst Read Mode
In the continuous burst read mode, the device outputs sequential burst data from the starting
address given and then wrap around to address 000000h when it reaches the highest addres-
sable memory location. The burst read mode will continue until the system drives CE# high,
RESET# low, or AVD# low in conjunction with a new address.
If the address being read crosses a 128-word line boundary and the subsequent word line is
not programming or erasing, additional latency cycles are required as shown in Tables 7.10–
If the address crosses a bank boundary while the subsequent bank is programming or eras-
ing, the device will provide read status information and the clock will be ignored. Upon
completion of status read or program or erase operation, the host can restart a burst read
operation using a new address and AVD# pulse.
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Write Set Configuration Register
Command and Settings:
Address 555h, Data D0h
Address X00h, Data CR
Load Initial Address
Address = RA
Read Initial Data
RD = DQ[15:0]
Read Next Data
RD = DQ[15:0]
Wait tIACC +
Programmable Wait State Setting
Wait X Clocks:
Additional Latency Due to Starting
Address, Clock Frequency, and
Boundary Crossing
End of Data?
Yes
Crossing
Boundary?
No
Yes
Completed
Delay X Clocks
Unlock Cycle 1
Unlock Cycle 2
RA = Read Address
RD = Read Data
Command Cycle
CR = Configuration Register Bits CR15-CR0
CR13-CR11 sets initial access time
(from address latched to
valid data) from 2 to 7 clock cycles
number of clocks required for X.
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