CLOCK CIRCUIT
S3C9654/C9658/P9658
7-2
MAIN OSCILLATOR LOGIC
To increase processing speed and to reduce clock noise, non-divided logic is implemented for the main oscillator
circuit. For this reason, very high resolution waveforms (square signal edges) must be generated in order for the
CPU to efficiently process logic operations.
CLOCK STATUS DURING POWER-DOWN MODES
The two power-down modes, Stop mode and Idle mode, affect clock oscillation as follows:
— In Stop mode, the main oscillator "freezes," halting the CPU and peripherals. The contents of the register file
and current system register values are retained.
RESET operation releases the Stop mode, and starts the
oscillator.
— In Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt control and the timer. The
current CPU status is preserved, including stack pointer, program counter, and flags. Data in the register file
is retained. Idle mode is released by a
RESET or by an interrupt (external or internally-generated).
SYSTEM CLOCK CONTROL REGISTER (CLKCON)
The system clock control register, CLKCON, is located in location D4H. It is read/write addressable and has the
following functions:
— Oscillator IRQ wake-up function enable/disable (CLKCON.7)
— Oscillator frequency divide-by value: non-divided, 2, 8, or 16 (CLKCON.4 and CLKCON.3)
The CLKCON register controls whether or not an external interrupt can be used to trigger a Stop mode release
(This is called the "IRQ wake-up" function). The IRQ wake-up enable bit is CLKCON.7.
After a
RESET, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and
the fOSC/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the
CPU clock speed to fOSC, fOSC/2 or fOSC/8.