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参数资料
| 型号： | S5K437CX03 |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1/4 Optical Size 640x480 (VGA) 2.8V CMOS Image Sensor |
| 中文描述： | 1 / 4光学尺寸640 × 480（VGA）的2.8V的CMOS图像传感器 |
| 文件页数： | 25/36页 |
| 文件大小： | 285K |
| 代理商： | S5K437CX03 |
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1/4 INCH VGA CMOS IMAGE SENSOR
S5K437CX
21
2. Analog to Digital Converter ( ADC)
The image sensor has an on-chip ADC. Two-channel column parallel ADC scheme is used for separated color
channel gain and offset control.
2-1. ADC resolution
The default value of ADC resolution is 10bit and can be changed to 8-bit or 9-bit depending on the ADC
Resolution Control Register (
adcres
). Lowering ADC resolution reduces the required minimum line time. When
the number of effective output bits is reduced, upper n-bits of output ports are valid and lower bits always have the
value of '0'.
2-2. Correlated Double Sampling (CDS)
The analog output signal of each pixel has some temporal random noise and fixed pattern noise caused by the
pixel reset action and the in-pixel amplifier offset deviation respectively. To eliminate those noise components, a
correlated double sampling(CDS) circuit should be used before converting the mode to digital. The output signal
is sampled twice - one for the reset level and one for the actual signal level sampling.
2-3. Programmable Gain and Offset Control
You can control the gain of individual color channel on the Programmable Gain Control
Registers (pgcr, pgcg1, pgcg2, pgcb
) and offset on Offset Control Registers (
offsr,
offsg1, offsg2, offsb
). If the Color Channel Separation Mode is disabled (
ccsm=0
),
pgcg1 and offsg1 change the gains and offsets for all channels. As the value increases
on the gain control register, the ADC conversion input range decreases and the gain
increases as shown in the following equation:
0
5
10
15
20
25
30
35
40
45
0
16
32
48
64
80
96
112
128
Programmable Gain Control
C
1
2
3
4
5
6
7
8
9
10
0
16
32
48
64
80
96
112
128
Programmable Gain Control
R
Channel Gain = 128 / (128
Programmable Gain Control Register Value[6:0])
Figure 6. Relative Channel Gain
R G1 R G1
G2
B G2 B
R G1 R G1
G2
B G2 B
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