参数资料
型号: S6B0716
厂商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 33 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
中文描述: 33的COM / 100赛格驱动
文件页数: 23/57页
文件大小: 816K
代理商: S6B0716
S6B0716
33COM/100SEG DRIVER & CONTROLLER FOR STN LCD
19
LCD DISPLAY CIRCUITS
Oscillator
This is completely on-chip oscillator and its frequency is nearly independent of V
DD
. This oscillator signal is used in
the voltage converter and display timing generation circuit.
* Test Condition: Temperature (25
°
C & 85
°
C), TEMPS=”L”, No Load
V
DD
vs. fosc
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
2.4
2.7
3.0
3.3
3.6
4.0
4.5
5.0
5.5
V
DD
[V]
fosc
[kHz]
1/33 Duty (25°C)
1/33 Duty (85°C)
Figure 9. V
DD
vs. f
OSC
Display Timing Generator Circuit
This circuit generates some signals to be used for displaying LCD. The display clock, CL, generated by oscillation
clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip
RAM is generated in synchronization with the display clock (CL) and the 100-bit display data is latched by the
display data latch circuit in synchronization with the display clock. The display data, which is read to the LCD driver,
is completely independent of the access to the display data RAM from the microprocessor. The display clock
generates an LCD AC signal (M) which enables the LCD driver to make a AC drive waveform, and also generates an
internal common timing signal and start signal to the common driver. Driving 2-frame AC driver waveform and
internal timing signal are shown in figure 10.
In a multiple-chip configuration, the slave chip requires the M, CL and DISP signals from the master. The table 12
shows the M, CL, and DISP status.
Table 12. Master and Slave Timing Signal Status
Operation mode
Oscillator
M
CL
DISP
ON (internal clock used)
OFF (external clock used)
-
Output
Output
Input
Output
Input
Input
Output
Output
Input
Master
Slave
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