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| 型号： | S71WS512N80BAWZZ0 |
| 厂商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆叠式多芯片产品（MCP）的闪存和移动存储芯片的CMOS 1.8伏特 |
| 文件页数： | 16/142页 |
| 文件大小： | 1996K |
| 代理商： | S71WS512N80BAWZZ0 |
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16
S29WSxxxN MirrorBit Flash Family For Multi-chip Products (MCP)
S71WS512NE0BFWZZ_00_ A1 June 28, 2004
A d v a n c e I n f o r m a t i o n
General Description
The WSxxxN is a 256 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode
Flash memory device, organized as 16 Mwords of 16 bits. This device uses a sin-
gle V
CC
of 1.65 to 1.95 V to read, program, and erase the memory array. A 9.0-
volt V
HH
on ACC may be used for faster program performance if desired. The de-
vice can be programmed in standard EPROM programmers.
At 66 MHz and 1.8V V
IO
, the device provides a burst access of 11.2 ns at 30 pF
with am initial latency of 69 ns at 30 pF. At 54 MHz and 1.8V V
IO
, the device pro-
vides a burst access of 13.5 ns at 30 pF with an initial latency of 69 ns at 30 pF.
The device operates within the industrial temperature range of -40°C to +85°C
or wireless temperature range of -25°C to +80°C. These devices are offered in
MCP compatible FBGA packages. See the product selector guide for details
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory space into sixteen banks. The device can improve over-
all system performance by allowing a host system to program or erase in one
bank, then immediately and simultaneously read from another bank, with zero
latency. This releases the system from waiting for the completion of program or
erase operations.
The device is divided as shown in the following table:
The VersatileIO (V
IO
) control allows the host system to set the voltage levels
that the device generates at its data outputs and the voltages tolerated at its
data inputs to the same voltage level that is asserted on the V
IO
pin.
The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#)
and Output Enable (OE#) to control asynchronous read and write operations.
For burst operations, the device additionally requires Ready (RDY), and Clock
(CLK). This implementation allows easy interface with minimal glue logic to a
Bank
Quantity of Sectors
(WS256N)
4/4/4
15/7/3
16/8/4
16/8/4
16/8/4
16/8/4
16/8/4
16/8/4
16/8/4
16/8/4
16/8/4
16/8/4
16/8/4
16/8/4
16/8/4
16/8/4
15/7/3
4/4/4
Sector Size
16 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
64 Kwords
16 Kwords
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
相关PDF资料 |
PDF描述 |
|---|---|
| S71WS512N80BAWZZ2 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAWZZ3 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ0 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ2 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ3 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S71WS512N80BAWZZ2 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BAWZZ3 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ0 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ2 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512N80BFEZZ3 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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