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| 型号： | S71WS512NA0BFWZZ0 |
| 厂商： | Spansion Inc. |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| 中文描述： | 堆叠式多芯片产品（MCP）的闪存和移动存储芯片的CMOS 1.8伏特 |
| 文件页数： | 5/142页 |
| 文件大小： | 1996K |
| 代理商： | S71WS512NA0BFWZZ0 |
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June 28, 2004 S71WS512NE0BFWZZ_00_A1
5
A d v a n c e I n f o r m a t i o n
AC CHARACTERISTICS
(Under Recommended Operating Conditions
unless otherwise noted) . . . . . . . . . . . . . . . . . . . . 110
ASYNCHRONOUS READ OPERATION (PAGE MODE) ................110
AC CHARACTERISTICS (Continued) . . . . . . . . 111
ASYNCHRONOUS WRITE OPERATION .............................................111
AC CHARACTERISTICS (Continued) . . . . . . . . 112
SYNCHRONOUS OPERATION - CLOCK INPUT (BURST MODE)
..................................................................................................................................112
SYNCHRONOUS OPERATION - ADDRESS LATCH (BURST MODE)
..................................................................................................................................112
AC CHARACTERISTICS (Continued) . . . . . . . . 113
SYNCHRONOUS READ OPERATION (BURST MODE) ................113
AC CHARACTERISTICS (Continued) . . . . . . . . 114
SYNCHRONOUS WRITE OPERATION (BURST MODE) ..............114
AC CHARACTERISTICS (Continued) . . . . . . . . 115
POWER DOWN PARAMETERS ...............................................................115
OTHER TIMING PARAMETERS .................................................................115
AC CHARACTERISTICS (Continued) . . . . . . . . 116
AC TEST CONDITIONS ...............................................................................116
AC MEASUREMENT OUTPUT LOAD CIRCUIT .................................116
TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . 117
Asynchronous Read Timing #1-1 (Basic Timing)...................................... 117
Asynchronous Read Timing #1-2 (Basic Timing) ......................................117
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 118
Asynchronous Read Timing #2 (OE# & Address Access) ...................118
Asynchronous Read Timing #3 (LB# / UB# Byte Access) ..................118
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 119
Asynchronous Read Timing #4 (Page Address Access after CE#1 Control
Access) ..................................................................................................................119
Asynchronous Read Timing #5 (Random and Page Address Access) 119
TIMING DIAGRAMS (Continued) . . . . . . . . . . 120
Asynchronous Write Timing #1-1 (Basic Timing) ...................................120
Asynchronous Write Timing #1-2 (Basic Timing) ...................................120
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 121
Asynchronous Write Timing #2 (WE# Control) ...................................121
Asynchronous Write Timing #3-1 (WE# / LB# / UB# Byte Write Con-
trol) ........................................................................................................................121
TIMING DIAGRAMS (Continued) . . . . . . . . . . 122
Asynchronous Write Timing #3-2 (WE# / LB# / UB# Byte Write Con-
trol) .......................................................................................................................122
Asynchronous Write Timing #3-3 (WE# / LB# / UB# Byte Write Con-
trol) .......................................................................................................................122
TIMING DIAGRAMS (Continued) . . . . . . . . . . 123
Asynchronous Write Timing #3-4 (WE# / LB# / UB# Byte Write Con-
trol) .......................................................................................................................123
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 124
Asynchronous Read / Write Timing #1-1 (CE#1 Control) ...................124
Asynchronous Read / Write Timing #1-2 (CE#1 / WE# / OE# Control)
..................................................................................................................................124
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 125
Asynchronous Read / Write Timing #2 (OE#, WE# Control) ........125
Asynchronous Read / Write Timing #3 (OE#, WE#, LB#, UB# Control)
..................................................................................................................................125
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 126
Clock Input Timing ..........................................................................................126
Address Latch Timing (Synchronous Mode) ............................................126
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 127
Synchronous Read Timing #1 (OE# Control) .........................................127
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 128
Synchronous Read Timing #2 (CE#1 Control) ........................................128
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 129
Synchronous Read Timing #3 (ADV# Control) .....................................129
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 130
Synchronous Write Timing #1 (WE# Level Control) ...........................130
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 131
Synchronous Write Timing #2 (WE# Single Clock Pulse Control) ..131
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 132
Synchronous Write Timing #3 (ADV# Control) ...................................132
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 133
Synchronous Write Timing #4 (WE# Level Control, Single Write) 133
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 134
Synchronous Read to Write Timing #1(CE#1 Control) .......................134
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 135
Synchronous Read to Write Timing #2(ADV# Control) ....................135
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 136
Synchronous Write to Read Timing #1 (CE#1 Control) ......................136
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 137
Synchronous Write to Read Timing #2 (ADV# Control) ..................137
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 138
POWER-UP Timing #1 ....................................................................................138
POWER-UP Timing #2 ...................................................................................138
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 139
POWER DOWN Entry and Exit Timing ..................................................139
Standby Entry Timing after Read or Write ..............................................139
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 140
Configuration Register Set Timing #1 (Asynchronous Operation) ...140
TIMING DIAGRAMS (Continued) . . . . . . . . . . . 141
Configuration Register Set Timing #2 (Synchronous Operation) .....141
Revision Summary
相关PDF资料 |
PDF描述 |
|---|---|
| S71WS512NA0BFWZZ3 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512NB0BAEZZ0 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512NB0BAEZZ2 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512NB0BAEZZ3 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512NB0BAIZZ0 | Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S71WS512NA0BFWZZ2 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512NA0BFWZZ3 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512NB0BAEZZ0 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512NB0BAEZZ2 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
| S71WS512NB0BAEZZ3 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt |
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