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参数资料
| 型号： | S72NS128ND0AFW722 |
| 厂商： | Spansion Inc. |
| 英文描述： | Based MCPs |
| 中文描述： | 基于MCP的 |
| 文件页数： | 10/17页 |
| 文件大小： | 310K |
| 代理商： | S72NS128ND0AFW722 |
8
S72NS-N Based MCPs
S72NS128_256ND0_00_B1 November 9, 2005
A d v a n c e I n f o r m a t i o n
3
Input/Output Descriptions
A23 – A0
DQ15 – DQ0
F-CE#
=
=
=
Flash Address inputs
Flash Data input/output
Flash Chip-enable input. Asynchronous relative to CLK for Burst
Mode
Flash Output Enable input. Asynchronous relative to CLK for Burst
mode.
Flash Write Enable input
Flash device power supply (1.7 V to 1.95 V)
Flash Input/Output Buffer power supply
Flash Ground
Flash ready output. Indicates the status of the Burst read. V
OL
=
data invalid. V
OH
= data valid.
Flash Clock. The first rising edge of CLK in conjunction with AVD#
low latches the address input and activates burst mode operation.
After the initial word is output, subsequent rising edges of CLK
increment the internal address counter. CLK should remain low
during asynchronous access.
Flash Address Valid input. Indicates to device that the valid address
is present on the address inputs. V
IL
= for asynchronous mode,
indicates valid address; for burst mode, causes starting address to
be latched on rising edge of CLK. V
IH
= device ignores address
inputs
Flash hardware reset input. V
IL
= device resets and returns to
reading array data
Flash hardware write protect input. V
IL
= disables program and
erase functions in the four outermost sectors
Flash accelerated input. At V
HH
, accelerates programming;
automatically places device in unlock bypass mode. At V
IL
, disables
all program and erase functions. Should be at V
IH
for all other
conditions.
DRAM Address inputs.
DRAM Data input/output
DRAM System Clock
DRAM Chip Select
DRAM Clock Enable
DRAM Bank Select
DRAM Row Address Strobe
DRAM Column Address Strobe
DRAM Data Input/Output Mask
DRAM Write Enable input
DRAM Ground
DRAM Input/Output Buffer ground
DRAM Input/Output Buffer power supply
DRAM device power supply
DRAM Upper Data Strobe, output with read data and input with
write data
DRAM Lower Data Strobe, output with read data and input with
write data
DDR Clock for negative edge of CLK
Reserved for Future Use
No Connect. Can be connected to ground or left floating.
Internal Test mode pin for DDR DRAM only. Do not apply any signal
on this pin. Can be connected to ground or left floating.
F-OE#
=
F-WE#
F-V
CC
F-V
CCQ
F-V
SS
F-RDY
=
=
=
=
=
F-CLK
=
F-AVD#
=
F-RST#
=
F-WP#
=
F-V
PP
=
D-A11 – D-A0
D-DQ15 – D-DQ0 =
D-CLK
D-CE#
D-CKE
D-BA1 – BA0
D-RAS#
D-CAS#
D-DM1 – D-DM0
D-WE#
D-V
SS
D-V
SSQ
D-V
CCQ
D-V
CC
D-UDQS
=
=
=
=
=
=
=
=
=
=
=
=
=
=
D-LDQS
=
D-CLK#
RFU
NC
D-TEST
=
=
=
=
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