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参数资料
| 型号： | S80960SA-16 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 16 MHz, RISC PROCESSOR, PQFP80 |
| 封装： | EIAJ, QFP-80 |
| 文件页数： | 4/39页 |
| 文件大小： | 2371K |
| 代理商： | S80960SA-16 |
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8
80960SA
Table 3. 80960SA Pin Description: Bus Signals (Sheet 1 of 2)
NAME
TYPE
DESCRIPTION
CLK2
I
SYSTEM CLOCK provides the fundamental timing for 80960SA systems. It is
divided by two inside the 80960SA to generate the internal processor clock.
A31:16
O
T.S.
ADDRESS BUS carries the upper 16 bits of the 32-bit physical address to memory.
It is valid throughout the burst cycle; no latch is required.
AD15:1, D0
I/O
T.S.
ADDRESS/DATA BUS carries the low order 32-bit addresses and 16-bit data to
and from memory. AD15:4 must be latched since the cycle following the address
cycle carries data on the bus.
A3:1
O
T.S.
ADDRESS BUS carries the word addresses of the 32-bit address to memory.
These three bits are incremented during a burst access indicating the next word
address of the burst access. Note that A3:1 are duplicated with AD3:1 during the
address cycle.
ALE
O
T.S.
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
asserted during a Ta cycle and deasserted before the beginning of the Td state. It is
active HIGH and floats to a high impedance state during a hold cycle (Th).
AS
O
T.S.
ADDRESS STATUS indicates an address state. AS is asserted every Ta state and
deasserted during the following Td state. AS is driven HIGH during reset.
W/R
O
T.S.
WRITE/READ specifies, during a Ta cycle, whether the operation is a write or read.
It is latched on-chip and remains valid during Td cycles.
DEN
O
T.S.
DATA ENABLE is asserted during Td cycles and indicates transfer of data on the
AD lines. The AD lines should not be driven by an external source unless DEN is
asserted. When DEN is asserted, outputs from the previous cycle are guaranteed
to be three-stated. In addition, DEN deasserted indicates inputs have been
captured; therefore input hold times can be disregarded. DEN is driven HIGH
during reset.
DT/R
O
T.S.
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from
the bus. It is low during Ta and Td cycles for a read or interrupt acknowledgment; it
is high during Ta and Td cycles for a write. DT/R never changes state when DEN is
asserted. DT/R is driven HIGH during reset.
READY
I
READY indicates that data on AD lines can be sampled or removed. If READY is
not asserted during a Td cycle, the Td cycle is extended to the next cycle by
inserting a wait state (Tw).
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
相关PDF资料 |
PDF描述 |
|---|---|
| S80960SB-10 | 32-BIT, 10 MHz, RISC PROCESSOR, PQFP80 |
| S80C186XL12 | 16-BIT, 12 MHz, MICROPROCESSOR, PQFP80 |
| S80C186XL25 | 16-BIT, 25 MHz, MICROPROCESSOR, PQFP80 |
| S80C186XL20 | 16-BIT, 20 MHz, MICROPROCESSOR, PQFP80 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S80960SB-16 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS |
| S80BH97(E)4-C WAF | 制造商:Intel 功能描述: |
| S80C154-12 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| S80C154-16 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| S80C154-20 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
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