- 您现在的位置：买卖IC网 > PDF目录98071 > S80C186XL25 (INTEL CORP) 16-BIT, 25 MHz, MICROPROCESSOR, PQFP80 PDF资料下载
参数资料
| 型号： | S80C186XL25 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, 25 MHz, MICROPROCESSOR, PQFP80 |
| 封装： | EIAJ, QFP-80 |
| 文件页数： | 5/48页 |
| 文件大小： | 762K |
| 代理商： | S80C186XL25 |
第1页第2页第3页第4页当前第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页
80C186XL80C188XL
Table 3 Pin Descriptions
(Continued)
Pin
Input
Output
Pin Description
Name
Type
States
SRDY
I
S(L)
Synchronous Ready informs the processor that the addressed
memory space or IO device will complete a data transfer The
SRDY pin accepts an active-HIGH input synchronized to CLKOUT
The use of SRDY allows a relaxed system timing over ARDY This
is accomplished by elimination of the one-half clock cycle required
to internally synchonize the ARDY input signal Connecting SRDY
high will always assert the ready condition to the CPU If this line is
unused it should be tied LOW to yield control to the ARDY pin
LOCK
O
H(Z)
LOCK output indicates that other system bus masters are not to
gain control of the system bus LOCK is active LOW The LOCK
R(Z)
signal is requested by the LOCK prefix instruction and is activated
at the beginning of the first data cycle associated with the
instruction immediately following the LOCK prefix It remains active
until the completion of that instruction No instruction prefetching
will occur while LOCK is asserted
S0
O
H(Z)
Bus cycle status S0 –S2 are encoded to provide bus-transaction
information
S1
R(1)
S2
Bus Cycle Status Information
S2
S1
S0
Bus Cycle Initiated
0
Interrupt Acknowledge
0
1
Read IO
0
1
0
Write IO
0
1
Halt
1
0
Instruction Fetch
1
0
1
Read Data from Memory
1
0
Write Data to Memory
1
Passive (no bus cycle)
S2 may be used as a logical MIO indicator and S1 as a DTR
indicator
HOLD
I
A(L)
HOLD indicates that another bus master is requesting the local bus
The HOLD input is active HIGH The processor generates HLDA
HLDA
O
H(1)
(HIGH) in response to a HOLD request Simultaneous with the
R(0)
issuance of HLDA the processor will float the local bus and control
lines After HOLD is detected as being LOW the processor will
lower HLDA When the processor needs to run another bus cycle it
will again drive the local bus and control lines
In Enhanced Mode HLDA will go low when a DRAM refresh cycle
is pending in the processor and an external bus master has control
of the bus It will be up to the external master to relinquish the bus
by lowering HOLD so that the processor may execute the refresh
cycle
NOTE
Pin names in parentheses apply to the 80C188XL
13
相关PDF资料 |
PDF描述 |
|---|---|
| S80C186XL20 | 16-BIT, 20 MHz, MICROPROCESSOR, PQFP80 |
| S80C188XL20 | 16-BIT, 20 MHz, MICROPROCESSOR, PQFP80 |
| S80C188XL12 | 16-BIT, 12 MHz, MICROPROCESSOR, PQFP80 |
| SB80C186XL25 | 16-BIT, 25 MHz, MICROPROCESSOR, PQFP80 |
| SB80C188XL25 | 16-BIT, 25 MHz, MICROPROCESSOR, PQFP80 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S80C188 | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:CMOS High-Integration 16-Bit Microprocessors |
| S80C188-12 | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:CMOS High-Integration 16-Bit Microprocessors |
| S80C188-16 | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:CMOS High-Integration 16-Bit Microprocessors |
| S80C188-20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| S80C18820BR | 制造商:AMD 功能描述:* |
发布紧急采购，3分钟左右您将得到回复。