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| 型号： | S80C188XL12 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, 12 MHz, MICROPROCESSOR, PQFP80 |
| 封装： | EIAJ, QFP-80 |
| 文件页数： | 5/48页 |
| 文件大小： | 762K |
| 代理商： | S80C188XL12 |
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80C186XL80C188XL
Table 3 Pin Descriptions
(Continued)
Pin
Input
Output
Pin Description
Name
Type
States
SRDY
I
S(L)
Synchronous Ready informs the processor that the addressed
memory space or IO device will complete a data transfer The
SRDY pin accepts an active-HIGH input synchronized to CLKOUT
The use of SRDY allows a relaxed system timing over ARDY This
is accomplished by elimination of the one-half clock cycle required
to internally synchonize the ARDY input signal Connecting SRDY
high will always assert the ready condition to the CPU If this line is
unused it should be tied LOW to yield control to the ARDY pin
LOCK
O
H(Z)
LOCK output indicates that other system bus masters are not to
gain control of the system bus LOCK is active LOW The LOCK
R(Z)
signal is requested by the LOCK prefix instruction and is activated
at the beginning of the first data cycle associated with the
instruction immediately following the LOCK prefix It remains active
until the completion of that instruction No instruction prefetching
will occur while LOCK is asserted
S0
O
H(Z)
Bus cycle status S0 –S2 are encoded to provide bus-transaction
information
S1
R(1)
S2
Bus Cycle Status Information
S2
S1
S0
Bus Cycle Initiated
0
Interrupt Acknowledge
0
1
Read IO
0
1
0
Write IO
0
1
Halt
1
0
Instruction Fetch
1
0
1
Read Data from Memory
1
0
Write Data to Memory
1
Passive (no bus cycle)
S2 may be used as a logical MIO indicator and S1 as a DTR
indicator
HOLD
I
A(L)
HOLD indicates that another bus master is requesting the local bus
The HOLD input is active HIGH The processor generates HLDA
HLDA
O
H(1)
(HIGH) in response to a HOLD request Simultaneous with the
R(0)
issuance of HLDA the processor will float the local bus and control
lines After HOLD is detected as being LOW the processor will
lower HLDA When the processor needs to run another bus cycle it
will again drive the local bus and control lines
In Enhanced Mode HLDA will go low when a DRAM refresh cycle
is pending in the processor and an external bus master has control
of the bus It will be up to the external master to relinquish the bus
by lowering HOLD so that the processor may execute the refresh
cycle
NOTE
Pin names in parentheses apply to the 80C188XL
13
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S80C188XL-16 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:16-Bit Microprocessor |
| S80C188XL20 | 功能描述:IC MPU 16-BIT 5V 20MHZ 80-MQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
| S80C188XL25 | 制造商:Intel 功能描述:MPU Intel186 CISC 16-Bit CHMOS 25MHz 80-Pin PQFP |
| S80C194 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:16-Bit Microcontroller |
| S80C196EA | 功能描述:IC MPU 16-BIT 5V 40MHZ 160-QFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:80C 其它有关文件:STM32F101T8 View All Specifications 特色产品:STM32 32-bit Cortex MCUs 标准包装:490 系列:STM32 F1 核心处理器:ARM? Cortex?-M3 芯体尺寸:32-位 速度:36MHz 连通性:I²C，IrDA，LIN，SPI，UART/USART 外围设备:DMA，PDR，POR，PVD，PWM，温度传感器，WDT 输入/输出数:26 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:10K x 8 电压 - 电源 (Vcc/Vdd):2 V ~ 3.6 V 数据转换器:A/D 10x12b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:36-VFQFN，36-VFQFPN 包装:托盘 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名称:497-9032STM32F101T8U6-ND |
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