参数资料
型号: S9S08SC4E0VTG
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: MICROCONTROLLER, PDSO16
封装: 0.65 MM PITCH, ROHS COMPLIANT, TSSOP-16
文件页数: 31/31页
文件大小: 765K
代理商: S9S08SC4E0VTG
Chapter 3 Electrical Characteristics
MC9S08SC4 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
9
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Eqn. 3-1
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected)
is:
PD = K ÷ (TJ + 273°C)
Eqn. 3-2
Solving Equation 3-1 and Equation 3-2 for K gives:
K = PD × (TA + 273°C) + θJA × (PD)
2
Eqn. 3-3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 3-1 and Equation 3-2
iteratively for any value of TA
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting
site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board,
and board thermal resistance.
2 Junction to Ambient Natural Convection
Table 3-4. ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
Unit
Human
Body
Series resistance
R1
1500
Ω
Storage capacitance
C
100
pF
Number of pulses per pin
3
Latch-up
Minimum input voltage limit
–2.5
V
Maximum input voltage limit
7.5
V
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PDF描述
S9S08SC4E0CTG MICROCONTROLLER, PDSO16
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