Appendix A Electrical Characteristics
MC9S12XE-Family Reference Manual Rev. 1.21
Freescale Semiconductor
1217
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
A.2
ATD Characteristics
This section describes the characteristics of the analog-to-digital converter.
A.2.1
ATD Operating Characteristics
The following constraints exist to obtain full-scale, full range results:
VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA.
This constraint exists since the sample buffer amplier can not drive beyond the power supply levels that
it ties to. If the input level goes outside of this range it will effectively be clipped.
Table A-15. ATD Operating Characteristics
A.2.2
Factors Inuencing Accuracy
Source resistance, source capacitance and current injection have an inuence on the accuracy of the ATD.
A further factor is that PortAD pins that are congured as output drivers switching.
Conditions are shown in Table A-4 unless otherwise noted, supply voltage 3.13V < VDDA < 5.5 V Num
C
Rating
Symbol
Min
Typ
Max
Unit
1
D Reference potential
Low
High
VRL
VRH
VSSA
VDDA/2
—
VDDA/2
VDDA
V
2
D Voltage difference VDDX to VDDA
VDDX
–2.35
0
0.1
V
3
D Voltage difference VSSX to VSSA
VSSX
–0.1
0
0.1
V
4
C Differential reference voltage1
1 Full accuracy is not guaranteed when differential voltage is less than 4.50 V
VRH-VRL
3.13
5.0
5.5
V
5
C ATD Clock Frequency (derived from bus clock via the
prescaler)
fATDCLk
0.25
—
8.3
MHz
6
P ATD Clock Frequency in Stop mode (internal generated
temperature and voltage dependent clock, ICLK)
0.6
1
1.7
MHz
7
D ADC conversion in stop, recovery time2
2 When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time tATDSTPRCV is required to switch back to bus clock
based ATDCLK when leaving Stop Mode. Do not access ATD registers during this time.
tATDSTPRC
V
—
1.5
us
8D
ATD Conversion Period3
12 bit resolution:
10 bit resolution:
8 bit resolution:
3 The minimum time assumes a sample time of 4 ATD clock cycles. The maximum time assumes a sample time of 24 ATD clock
cycles and the discharge feature (SMP_DIS) enabled, which adds 2 ATD clock cycles.
NCONV12
NCONV10
NCONV8
20
19
17
—
42
41
39
ATD
clock
Cycles