Chapter 7 Background Debug Module (S12XBDMV2)
MC9S12XE-Family Reference Manual Rev. 1.21
Freescale Semiconductor
291
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Figure 7-7 represents the BDM command structure. The command blocks illustrate a series of eight bit
times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles
in the high state. The time for an 8-bit command is 8
× 16 target clock cycles.1
Figure 7-7. BDM Command Structure
7.4.6
BDM Serial Interface
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode
select input which selects between normal and special modes of operation. After reset, this pin becomes
the dedicated serial interface pin for the BDM.
The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see
the following explanation.
The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on
the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is
transmitted or received. Data is transferred most signicant bit (MSB) rst at 16 target clock cycles per
bit. The interface times out if 512 clock cycles occur between falling edges from the host.
The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all
times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically
drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide
brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host
for transmit cases and the target for receive cases.
Hardware
Firmware
GO,
48-BC
BC = Bus Clock Cycles
Command
Address
150-BC
Delay
Next
DELAY
8 Bits
AT ~16 TC/Bit
16 Bits
AT ~16 TC/Bit
16 Bits
AT ~16 TC/Bit
Command
Address
Data
Next
Data
Read
Write
Read
Write
TRACE
Command
Next
Command
Data
76-BC
Delay
Next
Command
150-BC
Delay
36-BC
DELAY
Command
Data
Next
Command
TC = Target Clock Cycles