参数资料
型号: SAB-C161S-LM 3V AA
厂商: Infineon Technologies
文件页数: 50/75页
文件大小: 0K
描述: IC MICROCONTROLLER 16BIT MQFP80
标准包装: 850
系列: C16xx
核心处理器: C166
芯体尺寸: 16-位
速度: 20MHz
连通性: EBI/EMI,SPI,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 63
程序存储器类型: ROMless
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
振荡器型: 外部
工作温度: 0°C ~ 70°C
封装/外壳: 80-QFP
包装: 带卷 (TR)
其它名称: B161SLM3VAAXT
C161SLM3VAABAUMA1
C161SLM3VAABXUMA1
SABC161SLM3VAAXT
SP000014946
C161S
Timing Characteristics
Data Sheet
50
V1.0, 2003-11
Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
Table 15 describes, how these variables are to be computed.
Note: Please respect the maximum operating frequency of the respective derivative.
5.4
AC Characteristics
Table 15
Memory Cycle Variables
Description
Symbol
Values
ALE Extension
t
A
TCL
× <ALECTL>
Memory Cycle Time Waitstates
t
C
2TCL
× (15 - <MCTC>)
Memory Tristate Time
t
F
2TCL
× (1 - <MTTC>)
Table 16
Multiplexed Bus (Standard Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
t
A + tC + tF (120 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
Unit
Min.
Max.
Min.
Max.
ALE high time
t
5
CC 10 +
t
A
TCL - 10
+
t
A
ns
Address setup to ALE
t
6
CC 4 +
t
A
TCL - 16
+
t
A
ns
Address hold after ALE
t
7
CC 10 +
t
A
TCL - 10
+
t
A
ns
ALE falling edge to RD,
WR (with RW-delay)
t
8
CC 10 +
t
A
TCL - 10
+
t
A
ns
ALE falling edge to RD,
WR (no RW-delay)
t
9
CC -10 +
t
A
-10 +
t
A
ns
Address float after RD,
WR (with RW-delay)
t
10
CC –
6
6ns
Address float after RD,
WR (no RW-delay)
t
11
CC –
26
TCL + 6
ns
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