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参数资料
| 型号： | SAB-C167CR-L33M |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 33 MHz, MICROCONTROLLER, PQFP144 |
| 封装： | PLASTIC, MQFP-144 |
| 文件页数： | 80/89页 |
| 文件大小： | 1477K |
| 代理商： | SAB-C167CR-L33M |
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C167CR
C167SR
Electrical Parameters
Data Sheet
79
V3.3, 2005-02
Bus Cycle Control via READY Input
The duration of an external bus cycle can be controlled by the external circuitry via the
READY input signal.
Synchronous READY permits the shortest possible bus cycle but requires the input
signal to be synchronous to the reference signal CLKOUT.
Asynchronous READY puts no timing constraints on the input signal but incurs one
waitstate minimum due to the additional synchronization stage.
Notes (Valid also for Figure 20)
4. Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
5. READY sampled HIGH at this sampling point generates a READY controlled
waitstate, READY sampled LOW at this sampling point terminates the currently
running bus cycle.
6. These timings are given for test purposes only, in order to assure recognition at a
specific clock edge. If the Asynchronous READY signal does not fulfill the indicated
setup and hold times with respect to CLKOUT, it must fulfill
tc
27 in order to be safely
synchronized. Proper deactivation of READY is guaranteed if READY is deactivated
in response to the trailing (rising) edge of the corresponding command (RD or WR).
7. Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an
additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC
waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC
waitstate this delay is zero.
8. If the next following bus cycle is READY controlled, an active READY signal must be
disabled before the first valid sample point for the next bus cycle. This sample point
depends on the MTTC waitstate of the current cycle, and on the MCTC waitstates
and the ALE mode of the next following cycle. If the current cycle uses a multiplexed
bus the intrinsic MUX waitstate adds another CLKOUT cycle to the READY
deactivation time.
Table 20
READY Timing (Operating Conditions apply)
Parameter
Symbol
Limits
Unit
Min.
Max.
Input setup time to CLKOUT rising edge
Valid for: READY input
tc
25
CC
12
–
ns
Input hold time after CLKOUT rising edge
Valid for: READY input
tc
26
CC
0–ns
Asynchronous READY input low time6)
tc
27
CC
tc
5 + tc25
–ns
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SAB-C167CR-LM | 制造商:Siemens 功能描述:MicroController, 16-Bit, 144 Pin, Plastic, QFP |
| SABC167CRLM HA+ | 制造商:Infineon Technologies AG 功能描述: |
| SAB-C167CR-LM HA+ | 功能描述:16位微控制器 - MCU 16BIT ROM/ROMLESS RoHS:否 制造商:Texas Instruments 核心:RISC 处理器系列:MSP430FR572x 数据总线宽度:16 bit 最大时钟频率:24 MHz 程序存储器大小:8 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 封装 / 箱体:VQFN-40 安装风格:SMD/SMT |
| SABC167CRLM HA+TR | 制造商:Infineon Technologies AG 功能描述: |
| SAB-C167CR-LMBA | 制造商:Siemens 功能描述:Part Number Only |
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