参数资料
型号: SAF-C161RI-LM
厂商: INFINEON TECHNOLOGIES AG
元件分类: 微控制器/微处理器
英文描述: 16-BIT, 20 MHz, MICROCONTROLLER, PQFP100
封装: METRIC, PLASTIC, QFP-100
文件页数: 37/60页
文件大小: 926K
代理商: SAF-C161RI-LM
Semiconductor Group
42
1998-05-01
C161RI
Notes
1) V
AIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these
cases will be X000H or X3FFH, respectively.
2) The limit values for f
BC must not be exceeded when selecting the CPU frequency and the ADCTC setting.
3) This parameter includes the sample time t
S, the time for determining the digital result and the time to load the
result register with the conversion result.
Values for the basic clock
tBC depend on programming and can be taken from the table above.
This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.
4) TUE is tested at V
AREF =5.0 V, VAGND =0V, VDD = 4.9 V. It is guaranteed by design for all other voltages within
the defined voltage range.
The specified TUE is guaranteed only if an overload condition (see
IOV specification) occurs on maximum 2 not
selected analog input pins and the absolute sum of input overload currents on all analog input pins does not
exceed 10 mA.
5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within each conversion step. The maximum internal resistance results from the programmed conversion
timing.
6) Not 100% tested, guaranteed by design.
7) During the sample time the input capacitance C
I can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach its final voltage level within
tS.
After the end of the sample time
tS, changes of the analog input voltage have no effect on the conversion result.
Values for the sample time
tS depend on programming and can be taken from the table above.
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