参数资料
型号: SAF-C161S-LM 3V AA
厂商: Infineon Technologies
文件页数: 21/75页
文件大小: 0K
描述: IC MCU 16BIT ROM/LESS MQFP-80-7
标准包装: 1
系列: C16xx
核心处理器: C166
芯体尺寸: 16-位
速度: 20MHz
连通性: EBI/EMI,SPI,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 63
程序存储器类型: ROMless
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 80-QFP
包装: 剪切带 (CT)
其它名称: SAF-C161S-LM3VAACT
SAF-C161S-LM3VAACT-ND
SAF-C161S-LM3VAAINCT
C161S
Functional Description
Data Sheet
24
V1.0, 2003-11
3.9
Oscillator Watchdog
The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip
oscillator (either with a crystal or via external clock drive). For this operation the PLL
provides a clock signal which is used to supervise transitions on the oscillator clock. This
PLL clock is independent from the XTAL1 clock. When the expected oscillator clock
transitions are missing the OWD activates the PLL Unlock / OWD interrupt node and
supplies the CPU with the PLL clock signal. Under these circumstances the PLL will
oscillate with its basic frequency.
In direct drive mode the PLL base frequency is used directly (
f
CPU = 2 … 5 MHz).
In prescaler mode the PLL base frequency is divided by 2 (
f
CPU = 1 … 2.5 MHz).
Note: The CPU clock source is only switched back to the oscillator clock after a
hardware reset.
The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON.
In this case (OWDDIS = ‘1’) the PLL remains idle and provides no clock signal, while the
CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also
no interrupt request will be generated in case of a missing oscillator clock.
Note: At the end of a reset bit OWDDIS reflects the inverted level of pin RD at that time.
Thus the oscillator watchdog may also be disabled via hardware by (externally)
pulling the RD line low upon a reset, similar to the standard reset configuration via
PORT0.
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