参数资料
型号: SAF-C164CI-L25M
厂商: INFINEON TECHNOLOGIES AG
元件分类: 微控制器/微处理器
英文描述: 16-BIT, 25 MHz, MICROCONTROLLER, PQFP80
封装: 0.65 MM PITCH, METRIC, PLASTIC, QFP-80
文件页数: 66/79页
文件大小: 1314K
代理商: SAF-C164CI-L25M
C164CI/SI
C164CL/SL
Data Sheet
65
V2.0, 2001-05
AC Characteristics
Demultiplexed Bus
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 25 MHz
Variable CPU Clock
1 / 2TCL = 1 to 25 MHz
Unit
min.
max.
min.
max.
ALE high time
t5
CC
10 +
tA
TCL - 10
+
tA
ns
Address setup to ALE
t6
CC
4 +
tA
TCL - 16
+
tA
ns
ALE falling edge to RD,
WR (with RW-delay)
t8
CC
10 +
tA
TCL - 10
+
tA
ns
ALE falling edge to RD,
WR (no RW-delay)
t9
CC
-10 +
tA
-10
+
tA
ns
RD, WR low time
(with RW-delay)
t12 CC 30 + tC
2TCL - 10
+
tC
ns
RD, WR low time
(no RW-delay)
t13 CC 50 + tC
3TCL - 10
+
tC
ns
RD to valid data in
(with RW-delay)
t14 SR –
20 +
tC
2TCL - 20
+
tC
ns
RD to valid data in
(no RW-delay)
t15 SR –
40 +
tC
3TCL - 20
+
tC
ns
ALE low to valid data in
t16 SR –
40 +
tA + tC
3TCL - 20
+
tA + tC
ns
Address to valid data in
t17 SR –
50 +
2
tA + tC
4TCL - 30
+ 2
tA + tC
ns
Data hold after RD
rising edge
t18 SR 0
0
ns
Data float after RD rising
edge (with RW-delay1))
t20 SR –
26 +
2
tA + tF
1)
2TCL - 14
+ 22
tA
+
tF
ns
Data float after RD rising
edge (no RW-delay1))
t21 SR –
10 +
2
tA + tF
1)
TCL - 10
+ 22
tA
+
tF
ns
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