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| 型号： | SAF-C164SV-2R25F |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | PLASTIC, TQFP-64 |
| 文件页数： | 51/65页 |
| 文件大小： | 932K |
| 代理商： | SAF-C164SV-2R25F |
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C164SV
Data Sheet
51
V1.0, 2003-04
Preliminary
Sample time and conversion time of the C164SV’s A/D Converter are programmable.
Table 14 should be used to calculate the above timings.
The limit values for
fBC must not be exceeded when selecting ADCTC.
Timing Example for 10-bit Conversion:
Assumptions:
fCPU
= 25 MHz (i.e.
tCPU = 40 ns), ADCTC = 00B, ADSTC = 00B.
Basic clock
fBC
=
fCPU/4 = 6.25 MHz, i.e. tBC = 160 ns.
Sample time
tS
=
tBC × 8 = 1280 ns.
Conversion 10-bit
tC10
=
tS + 40 tBC + 2 tCPU = (1280 + 6400 + 80) ns = 7.8 s.
Timing Example for 12-bit Conversion:
Assumptions:
fCPU = 20 MHz (i.e. tCPU = 50 ns), ADCTC = 00B, ADSTC = 00B.
Basic clock
fBC
=
fCPU/4 = 5.0 MHz, i.e. tBC = 200 ns.
Sample time
tS
=
tBC × 8 = 1600 ns.
Conversion 10-bit
tC10
=
tS + 40 tBC + 2 tCPU = (1600 + 8000 + 100) ns = 9.7 s.
Conversion 12-bit
tC12
=
tS + 46 tBC + 2 tCPU = (1600 + 9200 + 100) ns = 10.9 s.
7) If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V
(i.e.
VAREF = VDD + 0.2 V) the maximum TUE is increased to ±3 LSB. This range is not 100% tested.
8) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within each conversion step. The maximum internal resistance results from the programmed conversion
timing.
9) Not 100% tested, guaranteed by design and characterization.
10) During the sample time the input capacitance C
AIN can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach its final voltage level within
tS.
After the end of the sample time
tS, changes of the analog input voltage have no effect on the conversion result.
Values for the sample time
Table 14
A/D Converter Computation Table
ADCON.15|14
(ADCTC)
A/D Converter
Basic Clock
fBC
ADCON.13|12
(ADSTC)
Sample time
tS
00
fCPU / 4
00
tBC × 8
01
fCPU / 2
01
tBC × 16
10
fCPU / 16
10
tBC × 32
11
fCPU / 8
11
tBC × 64
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|---|---|
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