参数资料
型号: SAF-XC2230L-20F66L
厂商: INFINEON TECHNOLOGIES AG
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PQFP64
封装: 0.50 MM PITCH, GREEN, PLASTIC, LQFP-64
文件页数: 41/113页
文件大小: 3160K
代理商: SAF-XC2230L-20F66L
XC2230L, XC2234L
XC2000 Family / Econo Line
Functional Description
PRELIMINARY
Data Sheet
29
V1.0, 2010-12
6 Kbytes of on-chip Data SRAM (DSRAM) are used for storage of general user data.
The DSRAM is accessed via a separate interface and is optimized for data access.
2 Kbytes of on-chip Dual-Port RAM (DPRAM) provide storage for user-defined
variables, for the system stack, and for general purpose register banks. A register bank
can consist of up to 16 word-wide (R0 to R15) and/or byte-wide (RL0, RH0, …, RL7,
RH7) General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bit addressable. When used by a GPR,
any location in the DPRAM is bit addressable.
1024 bytes (2
× 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are word-wide registers which are
used to control and monitor functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC2000 Family. In order to ensure
upward compatibility they should either not be accessed or written with zeros.
The on-chip Flash memory stores code, constant data, and control data. The
160 Kbytes of on-chip Flash memory consist of 1 module of 32 Kbytes (preferably for
data storage) and 1 module of 128 Kbytes. Each module is organized in 4-Kbyte sectors.
The uppermost 4-Kbyte sector of segment 0 (located in Flash module 0) is used
internally to store operation control parameters and protection information.
Each sector can be separately write protected1), erased and programmed (in blocks of
128 Bytes). The complete Flash area can be read-protected. A user-defined password
sequence temporarily unlocks protected areas. The Flash modules combine 128-bit
read access with protected and efficient writing algorithms for programming and erasing.
Dynamic error correction provides extremely high read data security for all read access
operations. Access to different Flash modules can be executed in parallel.
For Flash parameters, please see Section 4.5.
Memory Content Protection
The contents of on-chip memories can be protected against soft errors (induced e.g. by
radiation) by activating the parity mechanism or the Error Correction Code (ECC).
The parity mechanism can detect a single-bit error and prevent the software from using
incorrect data or executing incorrect instructions.
The ECC mechanism can detect and automatically correct single-bit errors. This
supports the stable operation of the system.
It is strongly recommended to activate the ECC mechanism wherever possible because
this dramatically increases the robustness of an application against such soft errors.
1) To save control bits, sectors are clustered for protection purposes, they remain separate for
programming/erasing.
相关PDF资料
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SAF-XC2264-72F66L 32-BIT, FLASH, 66 MHz, MICROCONTROLLER, PQFP100
SAK-XC2264-56F66L 32-BIT, FLASH, 66 MHz, MICROCONTROLLER, PQFP100
SAF-XC2387-72F66L 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PQFP144
SAF-XC2735X-72F80L RISC MICROCONTROLLER, PQFP64
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