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参数资料
型号： SAH-XC2261N-24F66L
厂商： INFINEON TECHNOLOGIES AG
元件分类： 微控制器/微处理器
英文描述： 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PQFP100
封装： 0.50 MM PITCH, GREEN, PLASTIC, LQFP-100
文件页数： 14/131页
文件大小： 1627K
代理商： SAH-XC2261N-24F66L
XC2261N/68N, XC2263N/64N/65N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet
110
V1.4, 2011-07
Variable Memory Cycles
External bus cycles of the XC226xN are executed in five consecutive cycle phases (AB,
C, D, E, F). The duration of each cycle phase is programmable (via the TCONCSx
registers) to adapt the external bus cycles to the respective external module (memory,
peripheral, etc.).
The duration of the access phase can optionally be controlled by the external module
using the READY handshake input.
This table provides a summary of the phases and the ranges for their length.
Note: The bandwidth of a parameter (from minimum to maximum value) covers the
whole operating range (temperature, voltage) as well as process variations. Within
a given device, however, this bandwidth is smaller than the specified range. This
is also due to interdependencies between certain parameters. Some of these
interdependencies are described in additional notes (see standard timing).
Note: Operating Conditions apply.
Table 32 is valid under the following conditions:
C
L= 20 pF; voltage_range= upper ;
voltage_range= upper
Table 31
Programmable Bus Cycle Phases (see timing diagrams)
Bus Cycle Phase
Parameter
Valid Values Unit
Address setup phase, the standard duration of this
phase (1 … 2 TCS) can be extended by 0 … 3 TCS
if the address window is changed
tpAB
1 … 2 (5)
TCS
Command delay phase
tpC
0 … 3
TCS
Write Data setup/MUX Tristate phase
tpD
0 … 1
TCS
Access phase
tpE
1 … 32
TCS
Address/Write Data hold phase
tpF
0 … 3
TCS
Table 32
External Bus Timing for Upper Voltage Range
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
Output valid delay for RD,
WR(L/H)
t
10 CC
713
ns
Output valid delay for
BHE, ALE
t
11 CC
714
ns
Address output valid delay
for A23 ... A0
t
12 CC
814
ns
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