参数资料
型号: SAK-C167SR-LM
厂商: INFINEON TECHNOLOGIES AG
元件分类: 微控制器/微处理器
英文描述: 16-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP144
封装: PLASTIC, MQFP-144
文件页数: 73/89页
文件大小: 1477K
代理商: SAK-C167SR-LM
C167CR
C167SR
Electrical Parameters
Data Sheet
73
V3.3, 2005-02
Table 19
External Bus Cycle Timing (Operating Conditions apply)
Parameter
Symbol
Limits
Unit
Min.
Max.
Output delay from CLKOUT falling edge
Valid for: address, BHE, early CS, write data out, ALE
tc
10
CC -2
11
ns
Output delay from CLKOUT rising edge
Valid for: latched CS, ALE low
tc
11
CC -2
6
ns
Output delay from CLKOUT rising edge
Valid for: WR low (no RW delay), RD low (no RW
delay)
tc
12
CC -2
8
ns
Output delay from CLKOUT falling edge
Valid for: RD/WR low (with RW delay), RD high (with
RW delay)
tc
13
CC -2
6
ns
Input setup time to CLKOUT falling edge
Valid for: read data in
tc
14
SR 14
ns
Input hold time after CLKOUT falling edge
Valid for: read data in1)
1) Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
of RD. Therefore the read data may be removed immediately after the rising edge of RD. Address changes
before the end of RD have also no impact on (demultiplexed) read cycles.
tc
15
SR 0
ns
Output hold time after CLKOUT falling edge
Valid for: address, BHE, early CS2)
2) Due to comparable propagation delays (at comparable capacitive loads) the address does not change before
WR goes high. The minimum output delay (
tc17min) is therefore the actual value of tc19.
tc
17
CC -2
6
ns
Output hold time after CLKOUT edge3)
Valid for: write data out
3) Not subject to production test - verified by design/characterization.
tc
18
CC -2
ns
Output delay from CLKOUT falling edge
Valid for: WR high
tc
19
CC -2
4
ns
Turn off delay after CLKOUT edge3)
Valid for: write data out
tc
20
CC –
7
ns
Turn on delay after CLKOUT falling edge3)
Valid for: write data out
tc
21
CC -5
ns
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相关代理商/技术参数
参数描述
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SAK-C167SR-LM HA+ TR 制造商:Infineon Technologies AG 功能描述:
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