参数资料
型号: SAK-XC2263M-72F80L
厂商: INFINEON TECHNOLOGIES AG
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100
封装: 0.50 MM PITCH, GREEN, PLASTIC, LQFP-100
文件页数: 74/133页
文件大小: 1755K
代理商: SAK-XC2263M-72F80L
XC2268M/67M, XC2265M/64M/63M
XC2000 Family / Base Line
Functional Description
Data Sheet
45
V2.1, 2011-07
This common memory space consists of 16 Mbytes organized as 256 segments of
64 Kbytes; each segment contains four data pages of 16 Kbytes. The entire memory
space can be accessed bytewise or wordwise. Portions of the on-chip DPRAM and the
register spaces (ESFR/SFR) additionally are directly bit addressable.
The internal data memory areas and the Special Function Register areas (SFR and
ESFR) are mapped into segment 0, the system segment.
The Program Management Unit (PMU) handles all code fetches and, therefore, controls
access to the program memories such as Flash memory and PSRAM.
The Data Management Unit (DMU) handles all data transfers and, therefore, controls
access to the DSRAM and the on-chip peripherals.
Both units (PMU and DMU) are connected to the high-speed system bus so that they can
exchange data. This is required if operands are read from program memory, code or
data is written to the PSRAM, code is fetched from external memory, or data is read from
or written to external resources. These include peripherals on the LXBus such as USIC
or MultiCAN. The system bus allows concurrent two-way communication for maximum
transfer performance.
Up to 32 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code
or data. The PSRAM is accessed via the PMU and is optimized for code fetches. A
section of the PSRAM with programmable size can be write-protected.
Up to 16 Kbytes of on-chip Data SRAM (DSRAM) are used for storage of general user
data. The DSRAM is accessed via a separate interface and is optimized for data access.
2 Kbytes of on-chip Dual-Port RAM (DPRAM) provide storage for user-defined
variables, for the system stack, and for general purpose register banks. A register bank
can consist of up to 16 word-wide (R0 to R15) and/or byte-wide (RL0, RH0, …, RL7,
RH7) General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bit addressable. When used by a GPR,
any location in the DPRAM is bit addressable.
Data SRAM
00’A000
H
00’DFFF
H
16 Kbytes
Reserved for DSRAM
00’8000
H
00’9FFF
H
8 Kbytes
External memory area
00’0000
H
00’7FFF
H
32 Kbytes
1) Accesses to the shaded areas are reserved. In devices with external bus interface these accesses generate
external bus accesses.
2) The areas marked with “<” are slightly smaller than indicated. See column “Notes”.
3) The uppermost 4-Kbyte sector of the first Flash segment is reserved for internal use (C0’F000
H to C0’FFFFH).
4) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
peripherals properly.
Table 8
XC226xM Memory Map (cont’d)
1)
Address Area
Start Loc.
End Loc.
Area Size
2)
Notes
相关PDF资料
PDF描述
SAK-XC2263M-56F80L 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100
SAF-XC2263M-104F80L 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100
SAH-XC2267M-104F80L 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100
SAH-XC2267M-72F80L 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100
SAF-XC2267M-104F80L 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100
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