参数资料
型号: SAK-XC2364B-24F40L
厂商: Infineon Technologies
文件页数: 10/24页
文件大小: 0K
描述: IC MCU 16BIT FLASH 100-LQFP
标准包装: 1,000
系列: XC23xxB
核心处理器: C166SV2
芯体尺寸: 16/32-位
速度: 40MHz
连通性: CAN,EBI/EMI,I²C,LIN,SPI,SSC,UART/USART,USI
外围设备: I²S,POR,PWM,WDT
输入/输出数: 76
程序存储器容量: 192KB(192K x 8)
程序存储器类型: 闪存
RAM 容量: 18K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 16x10b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 100-LQFP 裸露焊盘
包装: 带卷 (TR)
其它名称: SP000627180
optional
fIfo
Buffer
protocol asC
protocol ssC
protocol Xyz
data
handling
+ more
data
shifting
optional
fIfo
Buffer
protocol asC
protocol ssC
protocol Xyz
data
handling
+ more
data
shifting
pins
Common
B
us
Int
er
fac
e
usIC Channel n
usIC Channel 0
enhanced Communication
multiCan
d e s I gners C an no w C onf I gure universal serial interfaces
depending on their system’s requirements. whether uarT, ssC (spI compatible),
lIn, IIC or IIs, any interface is possible after a quick adjustment of the usIC module.
Each USIC Channel
Is capable of handling uarT, spI, lIn,
IIC and IIs
Is individually configurable
(incl. baud rate generation)
handles full duplex data transfers
has programmable rx and Tx fIfos
Can be reprogrammed on the fly
without chip reset
A USIC Module
Is a cluster of 2 independent,
identical usIC channels
up to 5 usIC modules available
(=10 channels)
universal serial Interface (usIC)
MultiCAN Features
full Can with Can 2.0B active
up to 6 independent Can nodes
up to 256 message objects
programmable acceptance filtering
data transfer rate up to 1mbit/s, indi-
vidually programmable for each node
powerful analysis capability
fIfo data handling support
automatic gateway support
flexible interrupt handling
C omple X appl IC a TI ons
increasingly require intelligent communi-
cation over the Can network. a Can gate-
way and a fIfo are only two examples
of what can easily be implemented with
XC2000’s enhanced multiCan module.
message
object
Buffer
256
objects
linked
list
Control
Can node 5
Can node 3
Can node 2
Can node 1
Can node 0
Can Control
Timing Control and synchronization
scheduler
schedule Timing data memory
TXdC5
rXdC5
multiCan module Kemel
Time-triggered extension
TXdC3
rXdC3
TXdC2
rXdC2
TXdC1
rXdC1
TXdC0
rXdC0
18
Enhanced Communication
Can node 4
TXdC4
rXdC4
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