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2001 Semtech Corp.
www.semtech.com
POWER MANAGEMENT
SC1144
PRELIMINARY
Applications Information - Output Voltage Table (Cont.)
FUNCTIONAL DESCRIPTION
The SC1144 is a programmable, high performance, multi-
phase controller designed for the most demanding DC/
DC converter applications in which transient response,
space, input ripple current and component form factor
and cost are paramount. The SC1144 based dc/dc con-
verter consists of four synchronized converters. The gate
drives to the converters are alternated sequentially by
the SC1144 allowing equal sharing of the load current
among the stages. The high clock frequency allows for
smaller inductor value and miniature surface mount, low
inductance output capacitors. Since each stage has
the output current, the conduction losses in each stage
are reduced by a factor of 1/16. Precision active trim-
ming ensures 1% matching of duty cycles among phases,
thus ensuring the heat and component stress is shared
equally. This allows use of lower cost components in
each phase and virtual elimination of heat sinks.
Fig. 1: V
OUT Ripple, VOUT = 2.0V, IOUT = 30A
Decoder/Bias Generator/PWM controller
The 8 MHz (max) clock is divided down to 2 MHz for four
phase operation by the clock decoder. The start of the
output pulses are time shifted 90 degrees by the de-
coder with respect to each other. The Bias Generator
generates the ramps to each phase by a precision
trimmed current source and on-chip capacitors. The
decoder, which is synchronized to the bias generator via
the master clock, phase shifts the ramps and enables
the PWM controller sequentially. A resistor from R
REF pin
to FBG programs the frequency and ramp time. The ramps
are then compared to the error amplifier output at the
high speed PWM comparator inputs. The oscillator mas-
ter clock frequency is programmed as follows:
Clock Freq=(8.2K/Rref)*8Mhz
Fig. 2: The four Gate Drives firing 90° out of phase.
V
OUT = 2.0V, IOUT = 10A
Error Amplifier
At the heart of the controller is an ultra-fast,
transconductance error amplifier. Since the output in-
ductor values can be selected to be a minimum, usually
less than a micro-Henry, the delays due to inductor ramp
time are minimized during transient load recovery. The
higher frequency of operation also allows use of much
smaller capacitance on the output. This means that the
dc/dc converter output capacitors hold Time is less.
The error amplifier must therefore respond extremely fast
Recover the Fort after a transient. The SC1144 error
amplifier recovers to its normal duty cycle after applica-
tion of a full load transient within 2 usec maximum, (largely
dependant on input and output capacitance) and usually
within 1usec. This minimizes undershoot and overshoot
during application of a transient. Operation at high fre-
quency minimizes the output inductor thus allowing faster
current ramp to the output capacitors.