参数资料
型号: SC16C554IB80,528
厂商: NXP Semiconductors
文件页数: 28/55页
文件大小: 0K
描述: IC UART QUAD SOT315-1
标准包装: 1
通道数: 4,QUART
FIFO's: 16 字节
电源电压: 2.5V,3.3V,5V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 80-LQFP
供应商设备封装: 80-LQFP(12x12)
包装: 标准包装
其它名称: 568-5954-6
Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 05 — 10 May 2004
34 of 55
9397 750 13132
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
When using software ow control the Xon/Xoff characters cannot be used for data transfer.
5
EFR[5]
Special Character Detect.
Logic 0 = Special character detect disabled (normal default condition).
Logic 1 = Special character detect enabled. The SC16C554/554D
compares each incoming receive character with Xoff2 data. If a match
exists, the received data will be transferred to FIFO and ISR[4] will be
set to indicate detection of special character. Bit-0 in the X-registers
corresponds with the LSB bit for the receive character. When this
feature is enabled, the normal software ow control must be disabled
(EFR[3-0] must be set to a logic 0).
4
EFR[4]
Enhanced function control bit. The content of IER[7:4], ISR[5:4], and
MCR[6] can be modied and latched. After modifying any bits in the
enhanced registers, EFR[4] can be set to a logic 0 to latch the new
values. This feature prevents existing software from altering or
overwriting the SC16C554/554D enhanced functions.
Logic 0 = Disable (normal default condition).
Logic 1 = Enable.
3:0
EFR[3:0]
Cont-3-0 Tx, Rx control. Logic 0 or cleared is the default condition.
Combinations of software ow control can be selected by programming
these bits. See Table 22.
Table 22:
Software ow control functions[1]
Cont-3
Cont-2
Cont-1
Cont-0
TX, RX software ow controls
0
X
No transmit ow control
1
0
X
Transmit Xon1/Xoff1
0
1
X
Transmit Xon2/Xoff2
1
X
Transmit Xon1 and Xon2/Xoff1 and Xoff2
X
0
No receive ow control
X
1
0
Receiver compares Xon1/Xoff1
X
0
1
Receiver compares Xon2/Xoff2
1
0
1
Transmit Xon1/Xoff1
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
1
Transmit Xon2/Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
1
Transmit Xon1 and Xon2/Xoff1 and Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
Table 21:
Enhanced Feature Register bits description…continued
Bit
Symbol
Description
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