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参数资料
| 型号： | SC16C650BIN40,112 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 11/48页 |
| 文件大小： | 0K |
| 描述： | IC UART SINGLE W/FIFO 40-DIP |
| 标准包装： | 9 |
| 通道数： | 1，UART |
| FIFO's： | 32 字节 |
| 电源电压： | 2.5V，3.3V，5V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 通孔 |
| 封装/外壳： | 40-DIP（0.600"，15.24mm） |
| 供应商设备封装： | 40-DIP |
| 包装： | 管件 |
| 其它名称： | 568-2045-5 935274389112 SC16C650BIN40 |
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SC16C650B_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 September 2009
19 of 48
NXP Semiconductors
SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels, and select the DMA mode.
7.3.1 DMA mode
7.3.1.1
Mode 0 (FCR bit 3 = 0)
Set and enable the interrupt for each single transmit or receive operation, and is similar to
the 16C450 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever an empty
transmit space is available in the Transmit Holding Register (THR). Receive Ready
(RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with
a character.
7.3.1.2
Mode 1 (FCR bit 3 = 1)
Set and enable the interrupt in a block mode operation. The transmit interrupt is set when
the transmit FIFO is below the programmed trigger level. The receive interrupt is set when
the receive FIFO lls to the programmed trigger level. However, the FIFO continues to ll
regardless of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long
as the FIFO ll level is above the programmed trigger level.
7.3.2 FIFO mode
Table 10.
FIFO Control Register bits description
Bit
Symbol
Description
7:6
FCR[7] (MSB),
FCR[6] (LSB)
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to Table 11.
5:4
FCR[5] (MSB),
FCR[4] (LSB)
Logic 0 or cleared is the default condition; TX trigger level = 16.
These bits are used to set the trigger level for the transmit FIFO
interrupt. The SC16C650B will issue a transmit empty interrupt when
the number of characters in FIFO drops below the selected trigger level.
Refer to Table 12.
3
FCR[3]
DMA mode select.
logic 0 = set DMA mode ‘0’ (normal default condition)
logic 1 = set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C650B is in the
16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there
are no characters in the transmit FIFO or transmit holding register, the
TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a
logic 1 after the rst character is loaded into the transmit holding
register.
Receive operation in mode ‘0’: When the SC16C650B is in 16C450
mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and
there is at least one character in the receive FIFO, the RXRDY pin will
be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SC16C652 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Dual UART with 32 bytes of transmit and receive FIFOs |
| SC16C652B | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:5V, 3.3 V and 2.5V dual UART, 5 Mbit/s (max.),with 32-byte FIFOs and infrared(IrDA) encoder/decoder |
| SC16C652BIB48 | 功能描述:UART 接口集成电路 16CB 2.5V-5V 2CH UART 32B FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC16C652BIB48,128 | 功能描述:UART 接口集成电路 16CB 2.5V-5V 2CH RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC16C652BIB48,151 | 功能描述:UART 接口集成电路 2CH. UART 32B FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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