参数资料
型号: SC16C752BIB48,128
厂商: NXP Semiconductors
文件页数: 24/47页
文件大小: 0K
描述: IC DUAL UART 64BYTE 48LQFP
标准包装: 2,000
通道数: 2,DUART
FIFO's: 64 字节
电源电压: 2.5V,3.3V,5V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 带卷 (TR)
其它名称: 935274411128
SC16C752BIB48-F
SC16C752BIB48-F-ND
SC16C752B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 — 30 November 2010
30 of 47
NXP Semiconductors
SC16C752B
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.13 Trigger Level Register (TLR)
This 8-bit register is pulsed to store the transmit and received FIFO trigger levels used for
DMA and interrupt generation. Trigger levels from 4 to 60 can be programmed with a
granularity of 4. Table 21 shows trigger level register bit settings.
Remark: TLR can only be written to when EFR[4] = logic 1 and MCR[6] = logic 1. If
TLR[3:0] or TLR[7:4] are logic 0, the selectable trigger levels via the FIFO Control
Register (FCR) are used for the transmit and receive FIFO trigger levels. Trigger levels
from 4 bytes to 60 bytes are available with a granularity of four. The TLR should be
programmed for N
4, where N is the desired trigger level.
When the trigger level setting in TLR is zero, the SC16C752B uses the trigger level setting
defined in FCR. If TLR has non-zero trigger level value, the trigger level defined in FCR is
discarded. This applies to both transmit FIFO and receive FIFO trigger level setting.
When TLR is used for RX trigger level control, FCR[7:6] should be left at the default state,
i.e., ‘00’.
7.14 FIFO ready register
The FIFO ready register provides real-time status of the transmit and receive FIFOs of
both channels.
The FIFO Rdy register is a read-only register that can be accessed when any of the two
UARTs is selected CSA or CSB = logic 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and
loopback is disabled. The address is 111.
Table 21.
Trigger Level Register bits description
Bit
Symbol
Description
7:4
TLR[7:4]
receive FIFO trigger levels (4 to 60), number of characters available
3:0
TLR[3:0]
transmit FIFO trigger levels (4 to 60), number of spaces available
Table 22.
FIFO Ready Register bits description
Bit
Symbol
Description
7:6
FIFO Rdy[7:6]
unused; always 0
5
FIFO Rdy[5]
receive FIFO B status. Related to DMA.
4
FIFO Rdy[4]
receive FIFO A status. Related to DMA.
3:2
FIFO Rdy[3:2]
unused; always 0
1
FIFO Rdy[1]
transmit FIFO B status. Related to DMA.
0
FIFO Rdy[0]
transmit FIFO A status. Related to DMA.
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