参数资料
型号: SC16C752BIB48,157
厂商: NXP Semiconductors
文件页数: 21/47页
文件大小: 0K
描述: IC UART DUAL W/FIFO 48-LQFP
产品培训模块: Stand-Alone UARTs
标准包装: 1,250
通道数: 2,DUART
FIFO's: 64 字节
电源电压: 2.5V,3.3V,5V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 托盘
产品目录页面: 828 (CN2011-ZH PDF)
其它名称: 568-1322
935274411157
SC16C752BIB48
SC16C752B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 — 30 November 2010
28 of 47
NXP Semiconductors
SC16C752B
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.9 Interrupt Identification Register (IIR)
The IIR is a read-only 8-bit register which provides the source of the interrupt in a
prioritized manner. Table 17 shows Interrupt Identification Register bit settings.
The interrupt priority list is shown in Table 18.
7.10 Enhanced Feature Register (EFR)
This 8-bit register enables or disables the enhanced features of the UART. Table 19
shows the Enhanced Feature Register bit settings.
Table 17.
Interrupt Identification Register bits description
Bit
Symbol
Description
7:6
IIR[7:6]
Mirror the contents of FCR[0]
5
IIR[5]
RTSn/CTSn LOW-to-HIGH change of state
4
IIR[4]
1 = Xoff/Special character has been detected
3:1
IIR[3:1]
3-bit encoded interrupt. See Table 18.
0
IIR[0]
Interrupt status.
logic 0 = an interrupt is pending
logic 1 = no interrupt is pending
Table 18.
Interrupt priority list
Priority
level
IIR[5]
IIR[4]
IIR[3]
IIR[2]
IIR[1]
IIR[0]
Source of the interrupt
1
0
0011
0Receiver Line Status error
2
0
0110
0Receiver time-out interrupt
2
0
0010
0
RHR interrupt
3
0
0001
0THR interrupt
4
0
0000
0Modem interrupt
5
0
1000
0Received Xoff signal/ special
character
6
1
0000
0CTSn, RTSn change of state from
active (LOW) to inactive (HIGH)
Table 19.
Enhanced Feature Register bits description
Bit
Symbol
Description
7EFR[7]
CTS flow control enable.
logic 0 = CTS flow control is disabled (normal default condition)
logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH
signal is detected on the CTSn pin.
6
EFR[6]
RTS flow control enable.
logic 0 = RTS flow control is disabled (normal default condition)
logic 1 = RTS flow control is enabled. The RTSn pin goes HIGH when the
receiver FIFO halt trigger level TCR[3:0] is reached, and goes LOW when the
receiver FIFO resume transmission trigger level TCR[7:4] is reached.
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