参数资料
型号: SC16C754BIA68,529
厂商: NXP Semiconductors
文件页数: 25/50页
文件大小: 0K
描述: IC UART QUAD 64BYTE 68PLCC
标准包装: 18
通道数: 4,QUART
FIFO's: 64 字节
电源电压: 2.5V,3.3V,5V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 68-LCC(J 形引线)
供应商设备封装: 68-PLCC
包装: 管件
其它名称: 935274938529
SC16C754BIA68-S
SC16C754BIA68-S-ND
SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
31 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.10 Enhanced Feature Register (EFR)
This 8-bit register enables or disables the enhanced features of the UART. Table 19 shows
the enhanced feature register bit settings.
7.11 Divisor latches (DLL, DLM)
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLM stores the most signicant part of the divisor. DLL stores
the least signicant part of the divisor.
Note that DLL and DLM can only be written to before Sleep mode is enabled, that is,
before IER[4] is set.
Table 19.
Enhanced feature register bits description
Bit
Symbol
Description
7
EFR[7]
CTS ow control enable.
logic 0 = CTS ow control is disabled (normal default condition)
logic 1 = CTS ow control is enabled. Transmission will stop when a HIGH
signal is detected on the CTS pin.
6
EFR[6]
RTS ow control enable.
logic 0 = RTS ow control is disabled (normal default condition)
logic 1 = RTS ow control is enabled. The RTS pin goes HIGH when the
receiver FIFO HALT trigger level TCR[3:0] is reached, and goes LOW when
the receiver FIFO RESUME transmission trigger level TCR[7:4] is reached.
5
EFR[5]
Special character detect.
logic 0 = special character detect disabled (normal default condition)
logic 1 = special character detect enabled. Received data is compared with
Xoff2 data. If a match occurs, the received data is transferred to FIFO and
IIR[4] is set to a logic 1 to indicate a special character has been detected.
4
EFR[4]
Enhanced functions enable bit.
logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4],
MCR[7:5].
logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5]
can be modied, that is, this bit is therefore a write enable.
3:0
EFR[3:0]
Combinations of software ow control can be selected by programming these
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