参数资料
型号: SC16C754BIB80,557
厂商: NXP Semiconductors
文件页数: 22/50页
文件大小: 0K
描述: IC UART QUAD W/FIFO 80-LQFP
产品培训模块: Stand-Alone UARTs
标准包装: 595
通道数: 4,QUART
FIFO's: 64 字节
电源电压: 2.5V,3.3V,5V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 80-LQFP
供应商设备封装: 80-LQFP(12x12)
包装: 管件
产品目录页面: 828 (CN2011-ZH PDF)
其它名称: 568-1207
935274939557
SC16C754BIB80
SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
29 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.8 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver
error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from LOW
to HIGH. The INT output signal is activated in response to interrupt generation. Table 16
shows the interrupt enable register bit settings.
[1]
IER[7:4] can only be modied if EFR[4] is set, that is, EFR[4] is a write enable. Re-enabling IER[1] will
cause a new interrupt if the THR is below the threshold.
Table 16.
Interrupt enable register bits description
Bit
Symbol
Description
7
CTS interrupt enable.
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt
6
RTS interrupt enable.
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt
5
Xoff interrupt.
logic 0 = disable the Xoff interrupt (normal default condition)
logic 1 = enable the Xoff interrupt
4
Sleep mode.
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode. See Section 6.7 “Sleep mode” for details.
3
IER[3]
Modem status interrupt.
logic 0 = disable the modem status register interrupt (normal default
condition)
logic 1 = enable the modem status register interrupt
2
IER[2]
Receive line status interrupt.
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
1
IER[1]
Transmit holding register interrupt.
logic 0 = disable the THR interrupt (normal default condition)
logic 1 = enable the THR interrupt
0
IER[0]
Receive holding register interrupt.
logic 0 = disable the RHR interrupt (normal default condition)
logic 1 = enable the RHR interrupt
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