参数资料
型号: SC16IS752IBS,151
厂商: NXP Semiconductors
文件页数: 15/60页
文件大小: 0K
描述: IC UART DUAL I2C/SPI 32-HVQFN
产品培训模块: Bridge Solutions
Stand-Alone UARTs
I²C Bus Fundamentals
特色产品: NXP - I2C Interface
标准包装: 490
特点: 低电流
通道数: 2,DUART
FIFO's: 64 字节
规程: RS232,RS485
电源电压: 2.5V, 3.3V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-HVQFN(5x5)
包装: 托盘
产品目录页面: 828 (CN2011-ZH PDF)
配用: 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
其它名称: 568-2236
935279288151
SC16IS752IBS-S
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
22 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.1 Receive Holding Register (RHR)
The receiver section consists of the Receive Holding Register (RHR) and the Receive
Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data
from the RX terminal. The data is converted to parallel data and moved to the RHR. The
receiver section is controlled by the Line Control Register. If the FIFO is disabled, location
zero of the FIFO is used to store the characters.
8.2 Transmit Holding Register (THR)
The transmitter section consists of the Transmit Holding Register (THR) and the Transmit
Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and
shifts it into the TSR, where it is converted to serial data and moved out on the TX
terminal. If the FIFO is disabled, location zero of the FIFO is used to store the byte.
Characters are lost if overflow occurs.
8.3 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver
error, RHR interrupt, THR interrupt, Modem Status, Xoff received, or CTS/RTS change of
state from LOW to HIGH. The IRQ output signal is activated in response to interrupt
generation. Table 11 shows Interrupt Enable Register bit settings.
Table 11.
Interrupt Enable Register bits description
Bit
Symbol
Description
7IER[7][1]
CTS interrupt enable.
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt
6IER[6][1]
RTS interrupt enable.
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt
5IER[5][1]
Xoff interrupt.
logic 0 = disable the Xoff interrupt (normal default condition)
logic 1 = enable the Xoff interrupt
4IER[4][1]
Sleep mode.
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode. See Section 7.6 “Sleep mode” for details.
3
IER[3]
Modem Status interrupt.
logic 0 = disable the Modem Status Register interrupt (normal default
condition)
logic 1 = enable the Modem Status Register interrupt
Remark: See IOControl register bit 1 or bit 2 (in Table 29) for the description
of how to program the pins as modem pins.
2
IER[2]
Receive Line Status interrupt.
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
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