参数资料
| 型号： | SC171MLTRT |
| 厂商： | Semtech |
| 文件页数： | 14/27页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 1A 10MLPD |
| 标准包装： | 1 |
| 系列： | EcoSpeed® |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.75 V ~ 5.23 V |
| 输入电压： | 3 V ~ 5.5 V |
| 频率 - 开关： | 200kHz ~ 1MHz |
| 电流 - 输出： | 1A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFDFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 10-MLPD（3x3） |
| 其它名称： | SC171MLDKR |
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SC171
Applications Information (continued)
I PEAK
I LOAD
I LIM
Time
Figure 7 — Valley Current Limit
Setting the valley current limit to a value of I LIM results
in a peak inductor current of ILIM plus the peak-to-peak
ripple current. In this situation, the average (load) current
through the inductor will be I LIM plus one half the peak-
to-peak ripple current.
Soft start of PWM Regulator
Soft start is achieved in the PWM regulator by using
an internal voltage ramp as the reference for the FB
comparator. The voltage ramp is generated using an
internal charge pump which drives the reference from
zero to 750mV in ~1.8mV increments, using an internal
~500kHz oscillator. When the ramp voltage reaches
750mV, the ramp is ignored and the FB comparator
switches over to a fixed 750mV threshold. During soft start
the output voltage tracks the internal ramp, which limits
the start-up inrush current and provides a controlled soft
start profile for a wide range of applications. Typical soft
start ramp time is 0.85ms.
During soft start the regulator turns off the low-side
MOSFET on any cycle if the inductor current falls to zero.
This prevents negative inductor current, allowing the
device to start into a pre-biased output up to 90% of the
targeted output. This soft start operation is implemented
even if FCM is selected. FCM operation is allowed only
after PGOOD is high.
? 2010 Semtech Corporation
Power Good Output
The power good (PGOOD) output is an open-drain output
which requires a pull-up resistor. When the output volt-
age is 10% below the nominal voltage, PGOOD is pulled
low. It is held low until the output voltage returns to the
nominal voltage. PGOOD is held low during soft start and
activated approximately 1ms after V OUT reaches regula-
tion. The total PGOOD delay is typically 2ms.
PGOOD will transition low if the V FB pin exceeds +20% of
nominal, which is also the over-voltage shutdown thresh-
old (900mV). PGOOD also pulls low if the EN/PSV pin is
low when VDD is present.
Output Over-Voltage Protection
Over-Voltage Protection (OVP) becomes active as soon
as the device is enabled. The threshold is set at 750mV +
20% (900mV). When V FB exceeds the OVP threshold, DL
latches high and the low-side MOSFET is turned on. DL
remains high and the controller remains off, until the EN/
PSV input is toggled or VDD is cycled. There is a 5μs delay
built into the OVP detector to prevent false transitions.
PGOOD is also low after an OVP event.
Output Under-Voltage Protection
When V FB falls to 75% of its nominal voltage (falls to
562.5mV) for eight consecutive clock cycles, the switcher
is shut off and the DH and DL drives are pulled low to turn
off the MOSFETs. The controller stays off until EN/PSV is
toggled or VDD is cycled.
VDD UVLO, and POR
Under-Voltage Lock-Out (UVLO) circuitry inhibits switch-
ing and tri-states the power FETs until VDD rises above
2.9V. An internal Power-On Reset (POR) occurs when
VDD exceeds 2.9V, which resets the fault latch and soft
start counter to begin the soft start cycle. The SC171 then
begins a soft start cycle. The PWM will shut off if VDD falls
below 2.7V.
14
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