参数资料
型号: SC183CULTRT
厂商: Semtech
文件页数: 18/20页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 2A 16MLPQ
标准包装: 1
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 3.3 V
输入电压: 2.9 V ~ 5.5 V
PWM 型: 电压模式
频率 - 开关: 2.5MHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-MLPQ
包装: 标准包装
供应商设备封装: 16-MLPQ-UT(3x3)
产品目录页面: 1357 (CN2011-ZH PDF)
其它名称: SC183CULDKR
SC183C
Applications Information (continued)
PCB Layout Considerations
The layout diagrams in Figure 5 and Figure 6 show a rec-
ommended PCB layout for a standard V OUT option and an
adjustable V OUT option, respectively. Fundamental layout
rules must be followed since the layout is critical for
VIN
L
VOUT
achieving the performance specified in the Electrical
Characteristics table. Poor layout can degrade the perfor-
mance of the DC-DC converter and can contribute to EMI
problems, ground bounce, and resistive voltage losses.
GND
CTLx
U1
C OUT
GND
Poor regulation and instability can result.
The following guidelines are recommended when devel-
oping a PCB layout:
(a) Top layer for standard volatge option
1. The input capacitor, C IN , provides a low impedance
loop for the pulsed currents present at the buck
VIN
GND
VOUT
converter’s inputs. C IN should therefore be placed as
close to the PVIN and PGND pins as possible, and no
more than 3mm away from the PVIN pin. Place the C IN
and SC183C on the same component side to eliminate
the use of vias between C IN and the device pins. Use
short wide traces or a copper plane to connect as
closely to the IC as possible. Use multiple vias for the
ground connection to the ground plane to reduce the
parasitic inductance. These measures will minimize
EMI and input voltage ripple by localizing the high
GND
(b) Bottom layer for standard voltage option
Figure 5 — Recommended PCB Top & Bottom Layer
Layout for Standard V OUT Option
frequency current pulses.
2. Keep the LX pin traces as short as possible to minimize
L
VOUT
C OUT
C IN
pickup of high frequency switching edges to other
parts of the circuit. C OUT and L should be connected as
close as possible between the LX and GND pins, with
a direct return to the GND pin from C OUT .
3. Route the output voltage feedback/sense path away
from the inductor and LX node to minimize noise and
magnetic interference.
4. Use a ground plane referenced to the SC183C PGND
pin. Use several vias to connect to the component
VIN
U1
GND GND
CTLx
(a) Top layer for adjustable voltage option
GND
side ground to further reduce noise and interference
on sensitive circuit nodes.
5. If possible, minimize the resistance from the VOUT
VIN
VOUT
and AGND pins to the load. This will reduce the
voltage drop on the ground plane and improve the
load regulation. And it will also improve the overall
GND
R FB2
R FB1
C FF
efficiency by reducing the copper losses on the output
and ground planes.
(b) Bottom layer for adjustable voltage option
Figure 6 — Recommended PCB Top & Bottom Layer
Layout for Adjustable V OUT Option
? 2010 Semtech Corp.
18
www.semtech.com
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SC185BULTRT 功能描述:IC REG BUCK SYNC 1V 4A 16MLPQ RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:250 系列:- 类型:降压(降压) 输出类型:固定 输出数:1 输出电压:1.2V 输入电压:2.05 V ~ 6 V PWM 型:电压模式 频率 - 开关:2MHz 电流 - 输出:500mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:6-UFDFN 包装:带卷 (TR) 供应商设备封装:6-SON(1.45x1) 产品目录页面:1032 (CN2011-ZH PDF) 其它名称:296-25628-2