参数资料
型号: SC194AMLTRT
厂商: Semtech
文件页数: 8/17页
文件大小: 0K
描述: IC REG BUCK ADJ 1A 10MLP
标准包装: 1
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 可调
输入电压: 2.7 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 1MHz
电流 - 输出: 1A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-VFDFN 裸露焊盘
包装: 标准包装
供应商设备封装: 10-MLP(3x3)
产品目录页面: 1357 (CN2011-ZH PDF)
其它名称: SC194AMLDKR
SC194A
POWER MANAGEMENT
Applications Information (Cont.)
In PSAVE mode V OUT is driven from a lower level to an
upper level by a switching burst. Once the upper level has
been reached the switching is stopped and the quiescent
current is reduced. V OUT falls from the upper to lower levels
in this low current state as the load current discharges
the output capacitor. The burst-to-off period in PSAVE will
decrease as the load current reduces.
The PSAVE switching burst frequency is controlled so that
the inductor current ripple is similar to that in PWM mode.
The minimum switching frequency during this period is
limited to 650kHz.
The SC194A automatically detects when to exit PSAVE
mode by monitoring V OUT . For the SC194A to exit PSAVE
mode, the load must be increased, causing V OUT to
decrease until the power save exit threshold is reached.
PRELIMINARY
100% Duty Cycle Operation
The 100% duty cycle mode may be selected by connecting
the MODE pin high. This will allow the SC194A to maintain
output regulation under low input voltage/high output
voltage conditions.
In 100% duty cycle operation, as the input supply drops
toward the output voltage, the PMOS on-time increases
linearly above the maximum value in ? xed-frequency
operation until the PMOS is active continuously. Once
the PMOS is switched on continuously, the output voltage
tracks the input voltage minus the voltage drop across
the PMOS power device and inductor according to the
following relationship:
V OUT = V I N ? I OUT × ( R DSP + R IND )
PSAVE levels are set high to minimize the undershoot
when exiting PSAVE. The lower PSAVE comparator level
is set +0.7% above V OUT , and the upper comparator level
at +1.5% above V OUT , with the exit threshold at -2% below
V OUT .
If PSAVE operation is required then a 22 μ F output
where,
V OUT
V IN
I OUT
R DSP
R IND
= Output voltage
= Input voltage
= Output current
= PMOS switch ON resistance
= Series resistance of the inductor
capacitor must be used.
Power Save Operation
Higher Load
The 100% duty cycle can only operate for a programmed
output voltage of 1.8V.
With an output voltage of 1.8V, 100% duty cycle mode will
only be required to maintain regulation if V IN falls below a
minimum value shown in the graph below.
1.5%
BURST
OFF
Applied
Minimum V IN for Fixed Frequency Operation Vs. R IND
3
0.7%
V OUT
-2%
PSAVE Mode at Light Load
PWM Mode at Medium/
High Load
2.95
2.9
2.85
Inductor Current
2.8
2.75
V OUT = 1.8V
0A
Time
2.7
0.05
0.1
0.15
0.2
I OUT =1A
0.25
0.3
Inductor DC R esistance ( Ω )
? 2006 Semtech Corp.
8
www.semtech.com
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PDF描述
SC194BMLTRT IC REG BUCK ADJ 1A 10MLP
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