参数资料
| 型号： | SC2595MLTRT |
| 厂商： | Semtech |
| 文件页数： | 6/12页 |
| 文件大小： | 0K |
| 描述： | IC DDR TERMINATION REG 16-MLPQ |
| 标准包装： | 1 |
| 应用： | 转换器，DDR |
| 输入电压： | 2.5 V ~ 5 V |
| 输出数： | 1 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-MLPQ |
| 包装： | 标准包装 |
| 产品目录页面： | 1358 (CN2011-ZH PDF) |
| 其它名称： | SC2595MLDKR |
SC2595
POWER MANAGEMENT
Application Information
Overview
PRELIMINARY
Application_2: Lower Power Loss Configuration
TL-2
f or SSTL -2
Double Data Rate (DDR) SDRAM was defined by JEDEC
1997. Its clock speed is the same as previous SDRAM
but data transfers speed is twice than previous SDRAM.
By now, the requirement voltage range is changed from
3.3V to 2.5V; the power dissipation is smaller than
SDRAM. For above reasons, it is very popular and widely
used in M/B, N/B, Video-cards, CD ROM drives, Disk
drives.
If power loss is a major concern, separated the PV CC form
the AV CC and the V DDQ will be a good choice. The PV CC can
operate at lower voltage (1.8V to 2.5V). If 2.5V voltage
is applied on AV CC and the V DDQ , but the source current is
lower due to the lower operating voltage applied on the
PV CC . Please find the relative test result in Figures 5, 11
and 12.
Cin2
1uF
Regarding the DDR power management solution, there
are two topologies can be selected for system design-
ers. One is switching mode regulator that has bigger sink/
source current capability, but the cost is higher and the
board space needed is bigger. Another solution is linear
mode regulator, which costs less, and needs the less
board space. For two DIMM motherboards, system de-
signers usually choose the linear mode for DDR power
management solution.
Applications
Csense
2.2uF
1
2
3
4
Cref
10nF
SC2595
NC VTT
GND PVCC
VSENSE AVCC
VREF VDDQ
8
7
6
5
1.8V to 2.5V
2.5V VDD Vin
R2 Cin1
R
68uF
Cddq
1uF
Cout1
220uF
VTT
1.25V
Cin2
10uF
T ypical Application Circuits & Wa v eforms
Figure 2: Lower power loss for SSTL-2 application
Two different application circuits are shown below in Fig-
ure 1 to Figure 2. Each circuit is designed for specific
condition. More details are described below. See Note
1. Below for recommended power up sequencing.
TL-2
Application_1: Standard SSTL -2 Application
The AV CC pins, the PV CC pin, and the V DDQ pin can be tied
together for SSTL-2 application. It only needs a 2.5V
power rail for normal operation. System designer can
save the PCB space and reduce the cost. Please refer
Notes:
(1) Power up of AV CC , PV CC and V DDQ supplies.
(a) The preferred mode of operation is when the
AV CC , PV CC and V DDQ pins are tied together to a
single supply.
(b) If and when AV CC , PV CC pins are tied to a supply
separate to that of the V DDQ supply pin; then
the V DDQ supply should lead AV CC , PV CC supply or
the V DDQ supply and the AV CC , PV CC supply should
rise simultaneously.
to figures 3 to 4 for test waveforms.
SC2595
1 8
NC VTT
2 7
GND PVCC
VDD
VTT
1.25V
(c) If the AV CC , PV CC and V DDQ supply pins are con
nected in a way such that, AV CC , PV CC supplies
precedes V DDQ supply; then V TT output precedes
V DDQ . This can cause the SDRAM device to latch-
up, which may cause permanent damage to the
SDRAM.
3
4
VSENSE
VREF
AVCC
VDDQ
6
5
R1
5.1
2.5V
Cin1
Cout1 Cout2
Csence Cref
68uF
220uF 10uF
2.2uF
10nF
Cin2
1uF
Figure 1: Standard SSTL-2 application
?200 9 Semtech Corp.
6
www.semtech.com
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