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| 型号： | SC2596SETRT |
| 厂商： | Semtech |
| 文件页数： | 11/14页 |
| 文件大小： | 0K |
| 描述： | IC INTEGRTD DDR TERM REG 8-SOIC |
| 标准包装： | 1 |
| 应用： | 转换器，DDR |
| 输入电压： | 2.3 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 0.9V，1.25V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm Width）裸露焊盘 |
| 供应商设备封装： | 8-SOIC-EP |
| 包装： | 标准包装 |
| 产品目录页面： | 1358 (CN2011-ZH PDF) |
| 其它名称： | SC2596SEDKR |
SC2596
POWER MANAGEMENT
Application Information (Cont.)
Application_5: Bode Plot of an all ceramic capacitor solution in Figure 5.
Figure 6: Bode Plot of an all ceramic capacitor application
The phase margin is 72° and the bandwidth is around 1MHz, where: AVCC=3.3V, PVCC=VDDQ=1.8V, VTT=0.9V,
IOUT=380mA, COUT=10uF & 100mhom. For this application, we further measured the corresponding phase
margins for different output capacitor values and ESR values at designed sourcing and sinking currents in
Figure 7.
Phase Margin vs External ESR
90.00
80.00
IO=380mA_Soure
120.00
100.00
IO=380mA_SINK
70.00
80.00
60.00
Cout=4.7uF
60.00
Cout=4.7uF
50.00
40.00
30.00
20.00
10.00
0.00
Cout=10uF
Cout=22uF
40.00
20.00
0.00
-20.00
-40.00
Cout=10uF
Cout=22uF
10mR
50mR
100mR
200mohm
10mR
50mR
100mR
200mohm
Figure 7: Phase margin vs external ESR values for different output ceramic capacitor values
Layout guidelines
1) The SOIC8-EDP package of SC2596 can improve the thermal impedance ( θ JC ) significantly. A suitable thermal
pad should be add when PCB layout. Some thermal vias are required to connect the thermal pad to the PCB
ground layer. This will improve the thermal performance. Please refer to the recommanded landing pattern.
2) To increase the noise immunity, a ceramic capacitor of 100nF is required to decouple the V REF pin with the
shortest connection trace.
3) To reduce the noise on input power rail for standard SSTL-2 application, a 100 μ F low ESR capacitor and a 1 μ F
ceramic capacitor capacitor have to be used on the input power rail with shortest possible connection.
4) VTT output copper plane should be as large as possible. A 4.7uF to 10 μ F capacitor have to be used to
decouple the VTT pin.
5) The trace between VSENSE pin and VTT rail should be as short as possible and put a 10nF ~100nF capacitor
close this vsense pin.
? 2009 Semtech Corp.
11
www.semtech.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SC2596STRT | 功能描述:IC INTEGRTD DDRII TERM REG 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| SC25A | 制造商:GXELECTRONICS 制造商全称:Gaomi Xinghe Electronics Co., Ltd. 功能描述:High current capability |
| SC25B | 制造商:GXELECTRONICS 制造商全称:Gaomi Xinghe Electronics Co., Ltd. 功能描述:High current capability |
| SC25D | 制造商:GXELECTRONICS 制造商全称:Gaomi Xinghe Electronics Co., Ltd. 功能描述:High current capability |
| SC25-FM-M25 | 制造商:HellermannTyton 功能描述:SC25-FM-M25-NPB-ML-1 |
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