参数资料
| 型号： | SC2596STRT |
| 厂商： | Semtech |
| 文件页数： | 10/14页 |
| 文件大小： | 0K |
| 描述： | IC INTEGRTD DDRII TERM REG 8SOIC |
| 标准包装： | 1 |
| 应用： | 转换器，DDR |
| 输入电压： | 2.3 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 0.9V，1.25V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 标准包装 |
| 其它名称： | SC2596SDKR |
SC2596
POWER MANAGEMENT
Application Information (Cont.)
Application_2: Lower Power Loss Configuration for
SSTL-2
If power loss is a major concern, separating the PVCC
form AVCC and VDDQ will be a good choice (Figure 2).
The PVCC can operate at lower voltage (1.8V to 2.5V) if
2.5V voltage is applied on AVCC and the VDDQ, the source
current is lower due to the lower operating voltage ap-
plied on the PVCC.
PRELIMINARY
Application_4: High Source Current Configuration
If there is a need for VTT to source more current, espe-
cially for DDR-II applications, the system designer can tie
the AVCC and PVCC to 3.3V while has the VDDQ tie to
1.8V. This configuration can ensure more than 2A source
and sink capability from the VTT rail.
1
GND
SC2596
VTT
8
VTT/1.25V
1
GND
SC2596
VTT
8
VTT/0.9V
EN/2.5V
2
EN
PVCC
7
PVCC=2.5V
EN
2
EN
PVCC
7
AVCC/PVCC=3.3V
3
VSENSE
AVCC
6 VDDQ/AVCC=2.5V
3
VSENSE
AVCC
6
VREF/1.25V
4
VREF
VDDQ
5
VREF/0.9V
4
VREF
VDDQ
5
VDDQ=1.8V
Csense
CREF
CIN1
CIN2
COUT
Csense
CREF
CIN1
CIN2
COUT COUT
100nF
1M
100nF
1uF
100uF 220uF
100nF
1M
100nF
1uF
100uF 10uF
220uF
0
Figure 2: Lower power loss for SSTL-2(DDR-I).
Application_3: Low Power Loss Configuration for
SSTL-18(DDR-II)
If power loss is a major concern, setting the PVCC to be
2.5V will be a good choice (Figure 3). The PVCC can op-
erate at lower voltage. if 2.5V voltage is applied on AVCC
and PVCC, the source current is lower due to the lower
operating voltage applied on the PVCC.
0
Figure 4: High current set up for SSTL-18(DDR-II).
Application_5: All Ceramic Capacitor Configuration
For some pure ceramic output capacitor designs, one
needs to add small ESR in series with the output capaci-
tor in order to enhance stability margin. For example, an
100mohm external ESR is suggested to help improve
the phase margin for the circuit in Figure 5. Figure 6
shows the corresponding Bode plot.
1
GND
SC2596
VTT
8
VTT/0.9V
1 GND
SC2596
VTT 8
VTT/0.9V
EN
2
3
EN
VSENSE
PVCC
AVCC
7
6
AVCC/PVCC=2.5V
EN
2 EN
3 VSENSE
PVCC 7
AVCC 6
VDDQ/PVCC=1.8V
COUT
AVCC=3.3V
10uF
VREF/0.9V
4
VREF
VDDQ
5 VDDQ=1.8V
VREF/0.9V
4 VREF
VDDQ 5
Csense
CREF
CIN1
CIN2 COUT
Csense
CREF
CIN1
CIN2
CIN3
External R
100nF
1M
100nF
1uF
100uF 220uF
100nF
1M 100nF
1uF
1uF
10uF
100mOhm
0
Figure 3: Lower power loss for SSTL-18(DDR-II).
0
Figure 5: All ceramic capacitor configuration.
Notes:
(a) The preferred configuration for DDR-I applications is to tie AVCC and PVCC to VDDQ, which is typically 2.5V.
(b) If AVCC and PVCC rails are tied together, then the VDDQ cannot lead the AVCC and PVCC.
? 2009 Semtech Corp.
10
www.semtech.com
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