参数资料
型号: SC28L92A1A,518
厂商: NXP Semiconductors
文件页数: 62/73页
文件大小: 0K
描述: IC UART DUAL W/FIFO 44-PLCC
标准包装: 500
系列: IMPACT
特点: 故障启动位检测
通道数: 2,DUART
FIFO's: 16 字节
电源电压: 3.3V,5V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC
包装: 带卷 (TR)
其它名称: 935263293518
SC28L92A1A-T
SC28L92A1A-T-ND
65
2552K–AVR–04/11
ATmega329/3290/649/6490
ing inputs should be avoided to reduce current consumption in all other modes where the digital
inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
In this case, the pull-up will be disabled during reset. If low power consumption during reset is
important, it is recommended to use an external pull-up or pull-down. Connecting unused pins
directly to V
CC or GND is not recommended, since this may cause excessive currents if the pin is
accidentally configured as an output.
13.3
Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. Figure 13-5
shows how the port pin control signals from the simplified Figure 13-2 can be overridden by
alternate functions. The overriding signals may not be present in all port pins, but the figure
serves as a generic description applicable to all port pins in the AVR microcontroller family.
Figure 13-5. Alternate Port Functions(1)
Note:
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
clk
RPx
RRx
WRx
RDx
WDx
PUD
SYNCHRONIZER
WDx:
WRITE DDRx
WRx:
WRITE PORTx
RRx:
READ PORTx REGISTER
RPx:
READ PORTx PIN
PUD:
PULLUP DISABLE
clk
I/O:
I/O CLOCK
RDx:
READ DDRx
D
L
Q
SET
CLR
0
1
0
1
0
1
DIxn
AIOxn
DIEOExn
PVOVxn
PVOExn
DDOVxn
DDOExn
PUOExn
PUOVxn
PUOExn:
Pxn PULL-UP OVERRIDE ENABLE
PUOVxn:
Pxn PULL-UP OVERRIDE VALUE
DDOExn:
Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn:
Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn:
Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn:
Pxn PORT VALUE OVERRIDE VALUE
DIxn:
DIGITAL INPUT PIN n ON PORTx
AIOxn:
ANALOG INPUT/OUTPUT PIN n ON PORTx
RESET
Q
D
CLR
Q
D
CLR
Q
D
CLR
PINxn
PORTxn
DDxn
D
ATA
B
U
S
0
1
DIEOVxn
SLEEP
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP:
SLEEP CONTROL
Pxn
I/O
0
1
PTOExn
WPx
PTOExn:
Pxn, PORT TOGGLE OVERRIDE ENABLE
WPx:
WRITE PINx
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