- 您现在的位置：买卖IC网 > PDF目录98078 > SC28L92A1B-S (NXP SEMICONDUCTORS) 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQFP44 PDF资料下载
参数资料
| 型号： | SC28L92A1B-S |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQFP44 |
| 封装： | 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44 |
| 文件页数： | 9/73页 |
| 文件大小： | 336K |
| 代理商： | SC28L92A1B-S |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页
SC28L92_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 19 December 2007
17 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Counter/Timer upper register. These commands have slight differences depending on the
mode of operation. Please see the detail of the commands in Section 7.3.3 “Command
6.2.7 Time-out mode caution
When operating in the special time-out mode, it is possible to generate what appears to be
a false interrupt, i.e., an interrupt without a cause. This may result when a time-out
interrupt occurs and then, before the interrupt is serviced, another character is received,
i.e., the data stream has started again. (The interrupt latency is longer than the pause in
the data stream.) In this case, when a new character has been received, the counter/timer
will be restarted by the receiver, thereby withdrawing its interrupt. If, at this time, the
interrupt service begins for the previously seen interrupt, a read of the ISR will show the
Counter Ready bit not set. If nothing else is interrupting, this read of the ISR will return a
0x00 character. This action may present the appearance of a spurious interrupt.
6.2.8 Communications channels A and B
Each communications channel of the SC28L92 comprises a full-duplex asynchronous
receiver/transmitter (UART). The operating frequency for each receiver and transmitter
can be selected independently from the baud rate generator, the counter/timer, or from an
external input. The transmitter accepts parallel data from the CPU, converts it to a serial
bit stream, inserts the appropriate start, stop, and optional parity bits and outputs a
composite serial stream of data on the TxD output pin. The receiver accepts serial data on
the RxD pin, converts this serial input to parallel format, checks for start bit, stop bit, parity
bit (if any), or break condition and sends an assembled character to the CPU via the
receive FIFO. Three status bits (break received, framing and parity errors) are also
FIFOed with each data character.
6.2.9 Input port
The inputs to this unlatched 7-bit (6-bit for 68xxx mode) port can be read by the CPU by
performing a read operation at address 0xD. A HIGH input results in a logic 1 while a LOW
input results in a logic 0. D7 will always read as a logic 1. The pins of this port can also
serve as auxiliary inputs to certain portions of the DUART logic, modem and DMA.
Four change-of-state detectors are provided which are associated with inputs IP3, IP2,
IP1 and IP0. A HIGH-to-LOW or LOW-to-HIGH transition of these inputs, lasting longer
than 25
s to 50 s, will set the corresponding bit in the input port change register. The
bits are cleared when the register is read by the CPU. Any change of state can also be
programmed to generate an interrupt to the CPU.
The input port change of state detection circuitry uses a 38.4 kHz sampling clock derived
from one of the baud rate generator taps. This results in a sampling period of slightly more
than 25
s (this assumes that the clock input is 3.6864 MHz). The detection circuitry, in
order to guarantee that a true change in level has occurred, requires two successive
samples at the new logic level be observed. As a consequence, the minimum duration of
the signal change is 25
s if the transition occurs coincident with the rst sample pulse.
The 50
s time refers to the situation in which the change of state is just missed and the
rst change of state is not detected until 25
s later.
相关PDF资料 |
PDF描述 |
|---|---|
| SC3327S | LVTTL SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| SC3526S/TD | TTL SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| SC3527S/D | TTL SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| SC3529S/TD | TTL SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| SC68C198A1A-T | 8 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQCC84 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SC28L92A1BS,528 | 功能描述:UART 接口集成电路 3V-5V 1CH UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC28L92A1BS,551 | 功能描述:UART 接口集成电路 3V-5V 1CH UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC28L92A1BS,557 | 功能描述:UART 接口集成电路 3V-5V 1CH UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC28L92A1BS-F | 功能描述:UART 接口集成电路 3V-5V 1CH UART INTEL/MOT INTRF RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SC28L92A1BS-S | 功能描述:UART 接口集成电路 3V-5V 1CH UART INTEL/MOT INTRF RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。