参数资料
型号: SC4211STRT
厂商: Semtech
文件页数: 7/9页
文件大小: 0K
描述: IC REG LDO FIX/ADJ 1A 8-SOIC
标准包装: 1
稳压器拓扑结构: 正,固定式或可调式
输出电压: 0.5V,1V,可调
输入电压: 1.4 V ~ 6 V
电压 - 压降(标准): 0.2V @ 1A
稳压器数量: 1
电流 - 输出: 1A
电流 - 限制(最小): 1.1A
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm Width)裸露焊盘
供应商设备封装: 8-SOIC-EP
包装: 标准包装
产品目录页面: 1358 (CN2011-ZH PDF)
其它名称: SC4211SDKR
SC4211
POWER MANAGEMENT
Applications Information
Introduction
The SC4211 is intended for applications where high cur-
rent capability and very low dropout voltage are required.
It provides a very simple, low cost solution that uses very
little PCB real estate. Additional features include an en-
able pin to allow for a very low power consumption standby
Enable: Pulling this pin below 0.4V turns the regulator
off, reducing the quiescent current to a fraction of its
operating value. A pull up resistor up to 400kOhms should
be connected from this pin to the VIN pin in application
where supply voltages of Vin < 1.9V is required. For ap-
plications with higher voltages than 1.9V, EN pin could
be left open or connected to VIN.
mode, and a fully adjustable output.
Thermal Considerations
Component Selection
The power dissipation in the SC4211 is approximately
Input capacitor: A large bulk capacitance of about
≥ 10uF/A (output load) should be closely placed to the
input supply pin of the SC4211 to ensure that Vin does
equal to the product of the output current and the input
to output voltage differential:
not sag below 1.4V. Also a minimum of 4.7μF ceramic
capacitor is recommended to be placed directly next to
P D ≈ ( VIN ? VOUT
) ? I O
the Vin pin. This allows for the device being some dis-
tance from any bulk capacitance on the rail. Additionally,
The absolute worst-case dissipation is given by:
input droop due to load transients is reduced, improving
load transient response. Additional capacitance may be
P D(MAX) = ( VIN
(MAX)
? VOUT
(MIN)
) ? I
O(MAX)
+ VIN
(MAX)
? I Q(MAX)
added if required by the application.
Output capacitor: A minimum bulk capacitance of
≥ 10μF/A (output load), along with a 0.1μF ceramic de-
coupling capacitor is recommended. Increasing the bulk
capacitance will improve the overall transient response.
The use of multiple lower value ceramic capacitors in
parallel to achieve the desired bulk capacitance will not
cause stability issues. Although designed for use with ce-
ramic output capacitors, the SC4211 is extremely toler-
ant of output capacitor ESR values and thus will also
For a typical scenario, V IN = 3.3V ± 5%, V OUT = 2.8V and
I O = 1A, therefore:
V IN(MAX) = 3.465V, V OUT(MIN) = 2.744V and I Q(MAX) = 1.75mA,
Thus P D(MAX) = .722W.
Using this figure, and assuming T A(MAX) = 70°C, we can cal-
culate the maximum thermal impedance allowable to main-
tain T J ≤ 150°C:
work comfortably with tantalum output capacitors.
Noise immunity: In very electrically noisy environments,
it is recommended that 0.1μF ceramic capacitors be
R TH(J ? A)(MAX) =
( T J(MAX) ? T A(MAX) )
P D(MAX)
=
( 150 ? 70 ) = 110 ° C/W
.722
placed from IN to GND and OUT to GND as close to the
device pins as possible.
Internal voltage selection: By connecting the FB pin to
GND, an internal resistor divider will regulate the output
voltage to 1.0V. If the FB pin is connected directly to the
VO pin, the output voltage will be regulated to the 0.5V
internal reference.
External voltage selection resistors: The use of 1%
resistors, and designing for a current flow ≥ 10μA is
recommended to ensure a well regulated output (thus
R2 ≤ 50k ? ).
This should be achievable for the SOIC-8-EDP package
using PCB copper area to aid in conducting the heat away,
such as one square inch of copper connected to the ground
pins of the device. Internal ground/power planes and air
flow will also assist in removing heat. For higher ambient
temperatures it may be necessary to use additional cop-
per area.
? 2007 Semtech Corp.
7
www.semtech.com
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