参数资料
型号: SC900AMLTRT
厂商: Semtech
文件页数: 12/23页
文件大小: 0K
描述: IC REG LDO ADJ .2A/.15A 20-MLPQ
标准包装: 1
稳压器拓扑结构: 正,可调式
输出电压: 1.45 V ~ 3 V,1.75 V ~ 3.3 V
输入电压: 2.7 V ~ 5.5 V
电压 - 压降(标准): 0.2V @ 200mA,0.15V @ 150mA
稳压器数量: 5
电流 - 输出: 200mA(最小),150mA(最小),150mA(最小),150mA(最小),150mA(最小)
电流 - 限制(最小): 250mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-VFQFN 裸露焊盘
供应商设备封装: 20-MLPQ(4x4)
包装: 剪切带 (CT)
产品目录页面: 1358 (CN2011-ZH PDF)
其它名称: SC900AMLCT
SC900A
POWER MANAGEMENT
Applications Information (Cont.)
Layout Considerations
Layout is straightforward if you use the Gerber ? les on
page 21 as a reference. Notice that the input voltage feed
to the SC900A is on the bottom of the board and vias con-
nect this voltage track to the top of the board and then
to the SC900A itself. The input bypass can be one 4.7 μ F
capacitor, two 3.3 μ F capacitors, three 2.2 μ F capacitors or
? ve 1 μ F capacitors. The determining factor is how much
copper is available on the input voltage feed track and
LDO Reset Control Logic Table (Defaults are in Bold)
how much room is available. If the input voltage track is
very thin, then use ? ve 1 μ F capacitors placed very close
to the input pins of the SC900A. If the input track is fairly
thick, then you can use a single 4.7 μ F capacitor at the be-
ginning of the voltage feed track since a wider track has
less inductance per inch. The SC900AEVB has ? ve 1 μ F
capacitors, but these can be replaced with one 4.7 μ F in
place of C1 and opens in place of C9, C14, C15, and C16
(see page 20 for details).
Register
Name
Register
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LDO A
LDO B
0x00
0x01
X
X
Active
Shutdown
1 = ON
0 = OFF
Output Voltage Codes
Table A for LDOs A & B
Table B for LDOs C, D & E
LDO C
LDO D
LDO E
0x02
0x03
0x04
LDO Reset
Control
0x05
LDOPGD Pin ARST Pin
Reset Polarity Bit Reset Polarity Bit
LDOPGD Monitor Logic Bits
LDOPGD Delay Bits
LDO (A) Reset Delay Bits
On/Off Control
Register
0x06
X
X
X
ON/OFF Control
LDO E
ON/OFF Control
LDO D
ON/OFF Control
LDO C
ON/OFF Control
LDO B
ON/OFF Control
LDO A
1
ON
0
OFF
1
ON
0
OFF
1
ON
0
OFF
1
ON
0
OFF
1
ON
0
OFF
LDO Reset Control Logic Table (Defaults are in Bold)
Bit 7
Result
Bit 6
Result
Bit 5
Bit 4
Result
Bit 3
Bit 2
Result
Bit 1
Bit 0
Result
LDOPGD Pin Polarity
ARST Pin Polarity
LDOPGD Monitor Logic
LDOPGD Delay
ARST Delay
0
High: Power Fail
0
High: Reset
0
0
LDOs
0
0
150ms
0
0
150ms
Low: Power Good
Low: Power Good
A, C, D & E
Good
1
High: Power Good
1
High: Power Good
0
1
LDO E Good
0
1
100ms
0
1
50ms
Low: Power Fail
Low: Reset
1
1
0
1
LDO C Good
LDO D Good
1
1
0
1
50ms
0ms
1
1
0
1
100ms
0ms
Note:
Digital outputs are powered from INB, additionally LDOB must be on for operation of LDOPGD and ARST.
SC900A Slave Address
DEVICE TYPE IDENTIFIER
DEVICE ADDRESS
R/W
0
0
0
1
0
0
A0
X
? 2005 Semtech Corp.
12
www.semtech.com
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