- 您现在的位置：买卖IC网 > PDF目录11822 > SCC68692E1A44,518 (NXP Semiconductors)IC DUART 44PLCC PDF资料下载
参数资料
| 型号： | SCC68692E1A44,518 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 10/28页 |
| 文件大小： | 0K |
| 描述： | IC DUART 44PLCC |
| 标准包装： | 500 |
| 特点： | 故障启动位检测 |
| 通道数： | 2，DUART |
| FIFO's： | 3 位 |
| 电源电压： | 5V |
| 带并行端口： | 是 |
| 带自动流量控制功能： | 是 |
| 带故障启动位检测功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC |
| 包装： | 带卷 (TR) |
| 其它名称： | 935027030518 SCC68692E1A44-T SCC68692E1A44-T-ND |
第1页第2页第3页第4页第5页第6页第7页第8页第9页当前第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
Philips Semiconductors
Product data
SCC68692
Dual asynchronous receiver/transmitter (DUART)
2004 Mar 03
18
ISR[6] – Channel B Change In Break
This bit, when set, indicates that the Channel B receiver has detected
the beginning or the end of a received break. It is reset when the CPU
issues a Channel B ‘reset break change interrupt’ command.
ISR[5] – Channel B Receiver Ready or FIFO Full
The function of this bit is programmed by MR1B[6]. If programmed
as receiver ready, it indicates that a character has been received in
Channel B and is waiting in the FIFO to be read by the CPU. It is set
when the character is transferred from the receive shift register to
the FIFO and reset when the CPU reads the RHR. If after this read
there are more characters still in the FIFO the bit will be set again
after the FIFO is ‘popped’. If programmed as FIFO full, it is set when
a character is transferred from the receive holding register to the
receive FIFO and the transfer caused the Channel B FIFO to
become full; i.e., all three FIFO positions are occupied. It is reset
when the CPU reads the RHR. If a character is waiting in the
receive shift register because the FIFO is full, the bit will be set
again when the waiting character is loaded into the FIFO.
ISR[4] – Channel B Transmitter Ready
This bit is a duplicate of TxRDYB (SRB[2]).
ISR[3] – Counter Ready.
In the counter mode, this bit is set when the counter reaches
terminal count and is reset when the counter is stopped by a stop
counter command.
In the timer mode, this bit is set once each cycle of the generated
square wave (every other time that the counter/timer reaches zero
count). The bit is reset by a stop counter command. The command,
however, does not stop the counter/timer.
ISR[2] – Channel A Change in Break
This bit, when set, indicates that the Channel A receiver has
detected the beginning or the end of a received break. It is reset
when the CPU issues a Channel A ‘reset break change interrupt’
command.
ISR[1] – Channel A Receiver Ready Or FIFO Full
The function of this bit is programmed by MR1A[6]. If programmed
as receiver ready, it indicates that a character has been received in
Channel A and is waiting in the FIFO to be read by the CPU. It is set
when the character is transferred from the receive shift register to
the FIFO and reset when the CPU reads the RHR. If after this read
there are more characters still in the FIFO the bit will be set again
after the FIFO is ‘popped’. If programmed as FIFO full, it is set when
a character is transferred from the receive holding register to the
receive FIFO and the transfer caused the Channel A FIFO to
become full; i.e., all three FIFO positions are occupied. It is reset
when the CPU reads the RHR. If a character is waiting in the
receive shift register because the FIFO is full, the bit will be set
again when the ISR[0] and IMR waiting character is loaded into the
FIFO.
ISR[0] – Channel A Transmitter Ready
This bit is a duplicate of TxRDYA (SRA[2]).
IMR – Interrupt Mask Register
The programming of this register selects which bits in the ISR
causes an interrupt output. If a bit in the ISR is a ‘1’ and the
corresponding bit in the IMR is also a ‘1’ the INTRN output will be
asserted. If the corresponding bit in the IMR is a zero, the state of
the bit in the ISR has no effect on the INTRN output. Note that the
IMR does not mask the programmable interrupt outputs OP3–OP7
or the reading of the ISR.
CTUR and CTLR – Counter/Timer Registers
The CTUR and CTLR hold the eight MSBs and eight LSBs,
respectively, of the value to be used by the counter/timer in either
the counter or timer modes of operation. The minimum value which
may be loaded into the CTUR/CTLR registers is H‘0002’. Note that
these registers are write-only and cannot be read by the CPU.
In the timer (programmable divider) mode, the C/T generates a
square wave with a period of twice the value (in clock periods) of the
CTUR and CTLR. The waveform so generated is often used for a
data clock. The formula for calculating the divisor n to load to the
CTUR and CTLR for a particular 1X data clock is shown below:
n
+
counter clock frequency
16
2
baud rate desired
Often this division will result in a non-integer number; 26.3, for
example. One can only program integer numbers in a digital divider.
Therefore, 26 would be chosen. This gives a baud rate error of
0.3/26.3 which is 1.14%; well within the ability asynchronous mode
of operation.
If the value in CTUR and CTLR is changed, the current half-period
will not be affected, but subsequent half periods will be. The C/T will
not be running until it receives an initial ‘Start Counter’ command
(read at address A3–A0 = 1110). After this, while in timer mode, the
C/T will run continuously. Receipt of a start counter command (read
with A3–A0 = 1110) causes the counter to terminate the current
timing cycle and to begin a new cycle using the values in CTUR and
CTLR.
The counter ready status bit (ISR[3]) is set once each cycle of the
square wave. The bit is reset by a stop counter command (read with
A3–A0 = H‘F’). The command however, does not stop the C/T. The
generated square wave is output on OP3 if it is programmed to be
the C/T output.
In the counter mode, the C/T counts down the number of pulses
loaded into CTUR and CTLR by the CPU. Counting begins upon
receipt of a start counter command. Upon reaching terminal count
H‘0000’, the counter ready interrupt bit (ISR[3]) is set. The counter
continues counting past the terminal count until stopped by the CPU.
If OP3 is programmed to be the output of the C/T, the output
remains HIGH until terminal count is reached, at which time it goes
LOW. The output returns to the HIGH state and ISR[3] is cleared
when the counter is stopped by a stop counter command. The CPU
may change the values of CTUR and CTLR at any time, but the new
count becomes effective only on the next start counter commands. If
new values have not been loaded, the previous count values are
preserved and used for the next count cycle
In the counter mode, the current value of the upper and lower 8 bits
of the counter (CTU, CTL) may be read by the CPU. It is
recommended that the counter be stopped when reading to prevent
potential problems which may occur if a carry from the lower 8 bits
to the upper 8 bits occurs between the times that both halves of the
counter are read. However, note that a subsequent start counter
command will cause the counter to begin a new count cycle using
the values in CTUR and CTLR.
IVR – Interrupt Vector Register
This register contains the interrupt vector. The register is initialized
to H‘0F’ by RESET. The contents of the register are placed on the
data bus when the DUART responds to a valid interrupt
acknowledge cycle.
相关PDF资料 |
PDF描述 |
|---|---|
| FT2232HL-TRAY | IC USB HS DUAL UART/FIFO 64-LQFP |
| SC28L92A1A,512 | IC UART DUAL W/FIFO 44-PLCC |
| VI-B5B-IY | CONVERTER MOD DC/DC 95V 50W |
| D38999/20WD19PC | CONN RCPT 19POS WALL MNT W/PINS |
| ATMEGA169PV-8MCHR | MCU AVR 16KB FLASH 16MHZ 64QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SCC68692E1A44-T | 功能描述:UART 接口集成电路 5V IND. UART 2 CH. MOT INTERF. RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SCC68692E1F40 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Dual asynchronous receiver/transmitter DUART |
| SCC68692E1N40 | 功能描述:UART 接口集成电路 5V IND. UART 2 CH. MOT INTERF. RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SCC68692E1N40,602 | 功能描述:UART 接口集成电路 5V IND. UART 2 CH. RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| SCC7600003 | 制造商:Denon Electronics 功能描述:GRILL ASS'YSCC76 |
发布紧急采购，3分钟左右您将得到回复。