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参数资料
| 型号： | SCE5784 |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 元件分类： | 显示用LED |
| 英文描述： | 5X7 DOT MATRIX DISPLAY, HIGH EFFICIENCY GREEN, 4.57 mm |
| 封装： | PLASTIC, DIP-26 |
| 文件页数： | 7/14页 |
| 文件大小： | 208K |
| 代理商： | SCE5784 |
2001 OSRAM Opto Semiconductors Inc. San Jose, CA
SCE5780/1/2/3/4/5/6
www.inneon.com/opto 408-456-4000
OSRAM Opto Semiconductors GmbH & Co. OHG Regensburg, Germany
www.osram-os.com +49-941-202-7178
2
August 1, 2001-18
DESCRIPTION (continued)
The Clock I/O (CLK I/O) and Clock Select (CLKSEL) pins offer
the user the capability to supply a high speed external multiplex
clock. This feature can minimize audio in-band interference for
portable communication equipment or eliminate the visual syn-
chronization effects found in high vibration environments such
as avionic equipment. The prescaler function allows for a higher
speed external multiplex clock when set to divide by 16.
Maximum Ratings
VCC, Logic Supply Voltage (non-operating) ....... –0.5 to +7.0 Vdc
VLL, LED Supply Voltage (non-operating)............ –0.5 to 5.5 Vdc
Input Voltage Levels Relative
to Ground ............................................... –0.5 to VCC +0.5 Vdc
Operating Temperature (1) ................................. –40
°C to +85°C
Storage Temperature....................................... –40
°C to +100°C
Maximum Solder Temperature 0.063"
below Seating Plane, t<5 s ............................................260
°C
Relative Humidity at 85
°C ...................................................85%
Maximum Power Dissipation
70
°C ...............................................................................1.7 W
85
°C .............................................................................1.25 W
ESD (100 pF, 1.5 k
) ........................................................ 2.0 kV
Maximum Input Current ...............................................±100 mA
Note:
1)
For operation at high temperature, see Thermal Considerations.
Switching Specications
(over operating temperature range and VCC=4.5 V to 5.5 V)
Note:
TSDCW is the minimum time the SDCLK may be low or high.
The SDCLK period must be a minimum of 200 ns.
Symbol
Description
Min.
Units
TRC
Reset Active Time
600
ns
TLDS
Load Setup Time
50
ns
TDS
Data Setup Time
50
ns
TSDCLK
Clock Period
200
ns
TSDCW
Clock Width
70
ns
TLDH
Load Hold Time
0
ns
TDH
Data Hold Time
25
ns
TWR
Total Write Time
2.2
s
TBL
Time Between Loads
600
ns
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