- 您现在的位置：买卖IC网 > PDF目录69340 > SCF5250CAG120 (FREESCALE SEMICONDUCTOR INC) 32-BIT, 120 MHz, MICROPROCESSOR, PQFP144 PDF资料下载
参数资料
| 型号： | SCF5250CAG120 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 120 MHz, MICROPROCESSOR, PQFP144 |
| 封装： | 20 X 20 MM, 1.40 MM THICKNESS, 0.50 MM PITCH, LEAD FREE, QFP-144 |
| 文件页数： | 5/56页 |
| 文件大小： | 894K |
| 代理商： | SCF5250CAG120 |
第1页第2页第3页第4页当前第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页
SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
13
3.2.2
Read-Write Control
This signal indicates during any bus cycle whether a read or write is in progress. A low is write cycle and
a high is a read cycle.
3.2.3
Output Enable
The OE signal is intended to be connected to the output enable of asynchronous memories connected to
chip selects. During bus read cycles, the ColdFire processor will drive OE low.
3.2.4
Data Bus
The data bus (D[31:16]) is bi-directional and non-multiplexed. Data is registered by the SCF5250 on the
rising clock edge. The data bus uses a default configuration if none of the chip-selects or DRAM bank
match the address decode. All 16 bits of the data bus are driven during writes, regardless of port width or
operand size.
3.2.5
Transfer Acknowledge
The TA/GPIO12 pin is the transfer acknowledge signal.
3.3
SDRAM Controller Signals
The following SDRAM signals provide a glueless interface to external SDRAM. An SDRAM width of 16
bits is supported and can access as much as 32MB of memory. ADRAMs are not supported.
Table 3. SDRAM Controller Signals
SDRAM Signal
Description
Synchronous DRAM row address strobe
The SDRAS/GPIO59 active low pin provides a seamless interface to the RAS input
on synchronous DRAM
Synchronous DRAM Column Address
Strobe
The SDCAS/GPIO39 active low pin provides a seamless interface to CAS input on
synchronous DRAM.
Synchronous DRAM Write
The SDWE/GPIO38 active-low pin is asserted to signify that a SDRAM write cycle
is underway. This pin outputs logic ‘1’ during read bus cycles.
Synchronous DRAM Chip Enable
The SD_CS0/GPIO60 active-low output signal is used during synchronous mode
to route directly to the chip select of a SDRAM device.
Synchronous DRAM UDQM and LQDM
signals
The DRAM byte enables UDMQ and LDQM are driven by the SDUDQM/GPO53
and SDLDQM/GPO52 byte enable outputs.
Synchronous DRAM clock
The DRAM clock is driven by the BCLK/GPIO40 signal
Synchronous DRAM Clock Enable
The BCLKE active high output signal is used during synchronous mode to route
directly to the SCKE signal of external SDRAMs. This signal provides the clock
enable to the SDRAM.
相关PDF资料 |
PDF描述 |
|---|---|
| SCN2651C1N28 | 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP28 |
| SCN2661AC1A28-T | 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC28 |
| SCN2661AA1F28 | 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, CDIP28 |
| SCN68661AC1N28 | 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP28 |
| SCN68661AA1F28 | 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, CDIP28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SCF5250CPV120 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:SCF5250 Integrated ColdFire Microprocessor |
| SCF5250DAG120 | 制造商:Freescale Semiconductor 功能描述:AMADEUS PLUS - Bulk |
| SCF5250LAG100 | 功能描述:IC MPU COLDFIRE 100MHZ 144-LQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:SCF52xx 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:260 系列:73S12xx 核心处理器:80515 芯体尺寸:8-位 速度:24MHz 连通性:I²C，智能卡，UART/USART，USB 外围设备:LED，POR，WDT 输入/输出数:9 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:2K x 8 电压 - 电源 (Vcc/Vdd):2.7 V ~ 5.5 V 数据转换器:- 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:68-VFQFN 裸露焊盘 包装:管件 |
| SCF5250LPV100 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SCF5250PV120 | 制造商:Rochester Electronics LLC 功能描述:AMADEUS PLUS - Bulk |
发布紧急采购，3分钟左右您将得到回复。