参数资料
型号: SD-15900PG-11
厂商: DATA DEVICE CORP
元件分类: 位置变换器
英文描述: SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CPGA85
封装: 1.120 X 1.120 INCH, 0.110 INCH HEIGHT, CERAMIC, PGA-85
文件页数: 3/8页
文件大小: 190K
代理商: SD-15900PG-11
3
The Digital Combiner output is then rescaled by the Scaler and
made available to the outputs. The output port, OUT<1:22>, can
be read by an external device as a single word or as individual
bytes via control input signals ENHIGH, ENMID, and ENLOW.
The outputs are tri-state, allowing “logical-oring” of the individual
bytes for interface to 8-bit devices.
The Timing and Control section defines all of the timing and is
responsible for generating all of the output control signals as well
as the internal data strobes used to latch the input data. An
internal clock can be used for all timing by strapping CLKOUT to
CLKIN, or an external clock can be used by driving input CLKIN.
INTERFACING
FIGURE 2 shows a typical application using an SD-14620
Synchro/Resolver-to-Digital Converter and an SD-15900.
The eight Most Significant Bits (MSB’s) of angular information from
the coarse synchro/resolver converter, along with the eight Most
Significant Bits and eight Least Significant Bits (LSB’s) of the fine
converter are wired together as an 8-bit data bus, and are con-
nected to the 8-bit data bus input of the code converter SD-15900.
The Inhibit (INH) signal from the combiner is connected to both
the fine and coarse synchro/resolver converters Inhibit inputs.
The three Enable signals (COARSE, FINEHI, FINELO) from the
combiner are connected to the associated Enable pins on the
synchro/resolver converters, i.e., Enable Coarse MSB’s, Enable
Fine MSB’s, and Enable Fine LSB’s.
The Hold input to the combiner can be driven by user-designed
circuitry if it is necessary to momentarily freeze the angular infor-
mation from the combiner based on the specific application.
The CLKOUT of the combiner generates a free running clock of
approximately 8 MHz and can be connected to the CLKIN of the
combiner for stand alone self clocking applications. The CLKIN
is divided by eight to create the internal clock. If it is necessary
to synchronize the clock of the combiner with a user clock, the
user clock can be connected to the CLKIN of the combiner
instead of the combiner-generated CLKOUT. The stability of the
clock is not important to the combiner circuitry and is used only
to set the rate at which the combiner samples the data from the
two synchro/resolver converters. Sampling of the angular data
from the two synchro/resolver converters occurs at the internal
clock rate divided by eight.
FIGURE 2. SD-15900 TYPICAL APPLICATION
BITS 1..16
IN<1..8>
OUT <1..16>
+5V
S1 ch.A
S2 ch.A
S3 ch.A
S4 ch.A
RH ch.A
RL ch.A
S1 ch.B
S2 ch.B
S3 ch.B
RH ch.B
S4 ch.B
INH
EMA
EMB
ELB
RL ch.B
COARSE
FINE
SD-15900
SD-14620
VPP
VCC
RES_L
ENHIGH
ENLOW
ENMID
MODE
GND
CLKIN
CLKOUT
FINELO
FINEHI
COARSE
INH
HOLD
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