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参数资料
| 型号： | SD-15900PH-100 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 位置变换器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CPGA85 |
| 封装： | CERAMIC, PGA-85 |
| 文件页数： | 4/8页 |
| 文件大小： | 373K |
| 代理商： | SD-15900PH-100 |
4
LSB’s strobe the two previously loaded angular data values, as
well as the current LSB data is simultaneously transferred to the
input of the internal combining circuitry, and the resulting angle
is generated.
The resulting combined bits of angular data is then made avail-
able via three sets of tri-state buffers; the eight MSB’s, the eight
middle bits, and the six LSB’s. Each set of bits has its own sep-
arate enable line.
The Hold signal on the combiner allows the currently generated
angle to be frozen. The state of the Hold signal is sampled on
the rising edge of every clock cycle. If the sampled signal is high
the transfer of the angular data to the combining circuit will take
place as described above. If the sampled signal is low the data
transfer will be inhibited and the output angle will not be updat-
ed. Data will be valid 0.5 s after the next rising edge of the inter-
nal clock. This condition will persist until the Hold signal is
brought back to the high state.
The only time the angular output data from the combiner can
change is during the Fine LSB’s Strobe and Data Transfer time.
The settling time during this interval will be limited to a period of
approximately 0.5 s.
INTERNAL CLOCK
INHIBIT
ENABLE FINE LSB'S
FINE LSB'S STROBE
AND DATA TRANSFER
ENABLE FINE MSB'S
FINE MSB'S STROBE
ENABLE COURSE MSB'S
COURSE MSB'S STROBE
1 s
0.5 s
FIGURE 3. SD-15900 TIMING DIAGRAM
INHIBIT AND ENABLE TIMING
FIGURE 3 shows the timing relationships for the SD-15900.
The internal clock is generated in the combiner for the purpose
of running the internal state generator that controls the timing
and control of the circuitry. The frequency of this clock was cho-
sen to be approximately 1 MHz and it is not critical. The top line
of the timing diagram shows the relationship of the clock to the
remaining signals.
The second signal on the timing diagram shows the INH signal
going to the S/D converter. Every eight clock cycles this signal
will go low and inhibit the converter so that the current angles
can be extracted.
The Course MSB’s Enable will be asserted approximately 0.5 s
after the inhibit is asserted and the associated data is strobed
into the combiner at the mid-point of the enable (approximately
0.5 s after it goes low). The enable line is then raised back to
logic high.
The fine MSB’s Enable is asserted next and the data is similarly
loaded into the combiner.
The fine LSB’s Enable is then asserted and the associated data
is made available to the combiner. At the rising edge of the fine
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