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参数资料
| 型号： | SDC-14565-125S |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 位置变换器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DIP36 |
| 封装： | 1.900 X 0.780 INCH, 0.210 INCH HEIGHT, DOUBLE WIDTH, KOVAR, DIP-36 |
| 文件页数： | 1/12页 |
| 文件大小： | 196K |
| 代理商： | SDC-14565-125S |
SDC-14560
DESCRIPTION
The SDC-14560 is a series of high-reli-
ability synchro or resolver-to-digital con-
verters with user-programmable resolu-
tion of 10, 12, 14, or 16 bits. Other fea-
tures of the SDC-14560 are high-quali-
ty velocity output and hermetic seal.
User-programmable resolution has
been designed into the SDC-14560 to
increase the capabilities of modern
motion control systems. The precise
positioning attained at 16-bit resolu-
tion and fast tracking of a 10-bit
device are now available from one 36-
pin double DIP hybrid. Velocity output
(VEL) from the SDC-14560 is a
ground-based
voltage
of
0
to
±10 VDC with a linearity to 0.7%.
Output voltage is positive for an
increasing angle.
The
SDC-14560
series
accepts
broadband inputs: 360 Hz to 1 kHz, or
47 Hz to 1 kHz. The digital angle out-
put from the SDC-14560 is a natural
binary code, parallel positive logic
and
is
TTL/CMOS
compatible.
Synchronization to a computer is
accomplished via a converter busy
(CB) and an inhibit (INH) input.
APPLICATIONS
Because of its high reliability, accura-
cy, small size, and low power con-
sumption, the SDC-14560 is ideal for
the most stringent and severe indus-
trial and military ground or avionics
applications. All models are available
with MIL-PRF-38534 processing as a
standard option.
Designed with three-state output, the
SDC-14560 is especially well suited
for use with computer-based systems.
Among the many possible applica-
tions are radar and navigation sys-
tems, fire control systems, flight
instrumentation, and flight trainers or
simulators.
SYNCHRO-TO-DIGITAL CONVERTER
FEATURES
Programmable Resolution:
10, 12, 14 or 16 Bits
High-Quality Velocity Output
Eliminates Tachometer
Accuracy to ±1.3 Arc
Minutes
Small Size
Synchro or Resolver Input
Synthesized Reference
Eliminates 180° Lock-Up
S1
S2
S3
SOLID STATE SYNCHRO INPUT OPTION
ELECTRONIC
SCOTT T
SIN
θ
COS
θ
S1
S2
S3
SOLID STATE RESOLVER INPUT OPTION
SIN
θ
COS
θ
S4
SOLID STATE RESOLVER INPUT OPTION
SIN
θ
COS
θ
SIN
θ
COS
θ
INPUT OPTIONS
V
INTERNAL
DC
REFERENCE
CONDITIONER
SYNTHESIZED
REF
DEMOD
BIT DETECT
ERROR
PROCESSOR
HIGH ACCURACY
CONTROL
TRANSFORMER
INPUT OPTION
16-BIT CT
TRANSPARENT
LATCH
16-BIT OUTPUT
TRANSPARENT
LATCH
3 STATE
TTL BUFFER
3 STATE
TTL BUFFER
16-BIT U-D
COUNTER
EDGE
TRIGGERED
LATCH
VCO
INHIBIT
TRANSPARENT
LATCH
POWER
SUPPLY
CONDITIONER
DIGITAL
ANGLE
φ
+5 V
INH
EM
BITS 1-8
BITS 9-16
EL
S
RESOLUTION CONTROL
T
50 ns DELAY
0.4-1 s
+10 V
INTERNAL DC
REF V (+5 V)
+15
INH
CB
VEL
e
BIT
+15 V
-15 V
DIFF
GAIN
OF 2
DIFF
GAIN OF
2, 7
VEL
U
T
E
D
R
U
T
GAIN
e
SIN
(
θ-φ)
1 LSB ANTIJITTER FEEDBACK
REF IN
RL
RH
SIN
θ
COS
θ
Q
AB
RESOLVER
CONDITIONER
VOLTAGE
FOLLOWER
BUFFER
1987, 1999 Data Device Corporation
FIGURE 1. SDC-14560 BLOCK DIAGRAM
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