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| 型号： | SDC2800DUT3D |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2000 MHz, MICROPROCESSOR, CPGA453 |
| 封装： | OPGA-453 |
| 文件页数： | 12/102页 |
| 文件大小： | 3049K |
| 代理商： | SDC2800DUT3D |
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Chapter 2
Interface Signals
5
31994A—1August 2004
AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet
2
Interface Signals
This section describes the interface signals utilized by the
AMD Sempron processor model 10.
2.1
Overview
The AMD Athlon system bus architecture is designed to deliver
excellent data movement bandwidth for next-generation x86
platforms as well as the high-performance required by
enterprise -class application so ftware. The system bus
arch it ec t u re c o nsist s of t h re e high-s peed ch annels (a
unidirectional processor request channel, a unidirectional
probe channel, and a 64-bit bidirectional data channel),
source-synchronous clocking, and a packet-based protocol. In
addition, the system bus supports several control, clock, and
legacy signals. The interface signals use an impedance
controlled push-pull, low-voltage, swing-signaling technology
contained within the Socket A socket.
For more information, see “AMD Athlon System Bus Signals”
AMD Athlon and AMD Duron System Bus Specification,
order# 21902.
2.2
Signaling Technology
The AMD Athlon system bus uses a low-voltage, swing-signaling
technology, that has been enhanced to provide larger noise
margins, reduced ringing, and variable voltage levels. The
signals are push-pull and impedance compensated. The signal
inputs use differential receivers that require a reference
voltage (VREF). The reference signal is used by the receivers to
determine if a signal is asserted or deasserted by the source.
Termination resistors are not needed because the driver is
impedance-matched to the motherboard and a high impedance
reflection is used at the receiver to bring the signal past the
input threshold.
For more information about pins and signals, see Chapter 10,
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